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Title: US7265620: Wide-band high-gain limiting amplifier with parallel resistor-transistor source loads
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Country: US United States of America

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Inventor: Liu, Wing Faat; San Jose, CA, United States of America
Zhang, Michael Y.; Palo Alto, CA, United States of America

Assignee: Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: 2007-09-04 / 2005-07-06

Application Number: US2005000160730

IPC Code: Advanced: H03F 3/45;
Core: more...

ECLA Code: H03F3/45S1K; H03F1/48B; H03F1/48I; H03F3/45S1B1; H03F3/45S3B3A; H03F3/45S3K3A;

U.S. Class: 330/253;

Field of Search: 330/253,260

Priority Number:
2005-07-06  US2005000160730

Abstract:     An amplifier has a wide bandwidth and a high gain by using parallel loads. Each load has a load resistor and a load p-channel transistor in parallel. The drain voltages of differential n-channel transistors can be set by the load resistors, while switching current is provided by the load p-channel transistors. The parallel load provides a high impedance to the drain nodes yet still provides driving current. A transconductance stage with a pair of differential transistors and two parallel loads drives a shunt-shunt-feedback stage that has another pair of differential transistors and two more parallel loads. Shunt resistors between the gate and drain of the differential transistors in the shunt-shunt-feedback stage provide shunt feedback and low impedance. Several pairs of transconductance and shunt-shunt-feedback stages can be cascaded together. The cascaded amplifier may be used as a signal repeater.

Attorney, Agent or Firm: g Patent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Pascal, Robert; Wong, Alan

INPADOC Legal Status: None          Buy Now: Family Legal Status Report

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First Claim:
Show all 19 claims
    1. A wideband amplifier comprising:

a first differential input and a second differential input that are driven in opposite directions to carry data;

a transconductance stage that comprises:

a first differential transistor having a gate that receives the first differential input, the gate controlling current in a channel between a first inter-stage node and a first tail node;

a first load between a first supply and the first inter-stage node, the first load having a first resistor in parallel with a channel of a first load transistor;

a second differential transistor having a gate that receives the second differential input, the gate controlling current in a channel between a second inter-stage node and the first tail node;

a second load between the first supply and the second inter-stage node, the second load having a second resistor in parallel with a channel of a second load transistor;

a second stage that comprises:

a third differential transistor having a gate that receives the first inter-stage node, the gate controlling current in a channel between a first output node and a second tail node;

a third load between the first supply and the first output node, the third load having a third resistor in parallel with a channel of a third load transistor;

a fourth differential transistor having a gate that receives the second inter-stage node, the gate controlling current in a channel between a second output node and the second tail node; and

a fourth load between the first supply and the second output node, the fourth load having a fourth resistor in parallel with a channel of a fourth load transistor;

wherein the second stage further comprises:

a first shunt resistor coupled between the first inter-stage node and the first output node;

a second shunt resistor coupled between the second inter-stage node and the second output node,


    whereby the second stage is a shunt-shunt-feedback stage and whereby the first, second, third, and fourth loads each have a resistor and a transistor in parallel.


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Description: Show description

Forward References: Show 2 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (2)   |   Backward references (19)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 5pp US3832489  1974-08 Rallapalli  Digital Equipment Corporation BIDIRECTIONAL BUS REPEATER
Buy PDF- 11pp US4061970  1977-12 Magneron  E.L.A.P. Transmission system and repeater stations therefor
Buy PDF- 10pp US4123625  1978-10 Chow  Northern Telecom Limited Digital regenerator having improving noise immunity
Buy PDF- 9pp US4710724  1987-12 Connell et al.  Motorola, Inc. Differential CMOS comparator for switched capacitor applications
Buy PDF- 7pp US4956613  1990-09 Hosticka et al.  Siemens Aktiengesellschaft Differential amplifier having externally controllable power consumption
Buy PDF- 11pp US5046185  1991-09 Hirai et al.  Hitachi, Ltd. Regenerative repeater
Buy PDF- 5pp US5391981  1995-02 Masson  Thomson Composants Militaires et Spatiaux Current source adapted to allow for rapid output voltage fluctuations
Buy PDF- 14pp US5596299  1997-01 Persico et al.  Philips Electronics North America Corporation IF amplifier/limiter with positive feedback
Buy PDF- 22pp US5973558  1999-10 Date et al.  Matsushita Electric Industrial Co., Ltd. Differential amplifier circuit
Buy PDF- 13pp US6345390  2002-02 Eto et al.  Hitachi Denshi Kabushiki Kaisha Bidirectional digital signal transmission system and repeater for the same
Buy PDF- 9pp US6369652  2002-04 Nguyen et al.  Rambus Inc. Differential amplifiers with current and resistance compensation elements for balanced output
Buy PDF- 25pp US6680681  2004-01 Hsu et al.  International Business Machines Corporation High speed FIR transmitter
Buy PDF- 6pp US6816002  2004-11 Bruck  Tyco Electronics AMP GmbH Circuit arrangement for controlling a constant current through a load
Buy PDF- 15pp US6870425  2005-03 Leifso et al.  Research in Motion Limited System and method of amplifier gain control by variable bias and degeneration
Buy PDF- 19pp US6882295  2005-04 Leung  Silicon Labs Cp, Inc., High speed comparator for a SAR converter with resistor loading and resistor bias to control common mode bias
Buy PDF- 8pp US6906589  2005-06 Ikeda et al.  Niigata Seimitsu Co., Ltd. Multistaged amplification circuit
Buy PDF- 8pp US6992526  2006-01 Cheng  Wionics Research Apparatus and method for DC offset reduction
Buy PDF- 43pp US20040013182A1  2004-01 Tonietto et al.   Bit stream conditioning circuit having output pre-emphasis
Buy PDF- 47pp US20040091028A1  2004-05 Aronson et al.   Transceiver module and integrated circuit with dual eye openers and equalizer
       
Foreign References:
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PDF
Publication Date IPC Code Assignee   Title
Buy PDF JP05075359A2 1993-03  H03F 1/02 MATSUSHITA ELECTRON CORP DIFFERENTIAL AMPLIFIER CIRCUIT 


Continuity Data:
Application Number Filed Notes

US2005000160730 2005-07-06  is a related to the prior publication
     US20070008035A1 issued 2007-01-11  Wide-Band High-Gain Limiting Amplifier with Parallel Resistor-Transistor Source Loads


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