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Title: US7277337: Memory module with a defective memory chip having defective blocks disabled by non-multiplexed address lines to the defective chip
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Country: US United States of America

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17 pages

 
Inventor: Co, Ramon S.; Trabuco Canyon, CA, United States of America
Chen, Mike; Newport Coast, CA, United States of America
Sun, David; Irvine, CA, United States of America

Assignee: Kingston Technology Corp., Fountain Valley, CA, United States of America
other patents from KINGSTON TECHNOLOGY COMPANY (741845) (approx. 14)
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Published / Filed: 2007-10-02 / 2006-09-25

Application Number: US2006000309782

IPC Code: Advanced: G11C 29/00;
Core: more...

ECLA Code: G11C29/00R12;

U.S. Class: 365/200; 365/201;

Field of Search: 365/185.09 714/007

Priority Number:
2006-09-25  US2006000309782

Abstract:     A downgraded memory module has downgraded DRAM chips soldered to its substrate. The downgraded DRAM chips have a defective memory cell in a logical quadrant of the memory. A physical MSB is a row address present on a non-downgraded DRAM of size S but not used on a downgraded DRAM size S/2. The physical MSB and a second address pin are non-multiplexed address pins that do not carry column addresses. The physical MSB and the second address pin logically divided the DRAM into quadrants. Two good quadrants without defects are selected, and jumpers on the memory module drive the physical MSB and the second address pin with signals that select only these two quadrants and disable access to quadrants containing defects. DRAM chips can be marked or sorted into bins for combinations of good quadrants. Downgraded memory modules have all DRAM chips from the same bin that share jumper settings.

Attorney, Agent or Firm: Auvinen, Stuart T. ; gPatent LLC ;

Primary / Asst. Examiners: Nguyen, Tan T.;

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 23 claims
    1. A downgraded memory module comprising:

a substrate having wiring traces formed thereon for conducting signals;

contact pads along a lower edge of the substrate, the contact pads for mating with a memory module socket on a motherboard;

memory chips mounted to the substrate, the memory chips having address, data, and control inputs that are directly connected to the contact pads or are buffered from the contact pads by a buffer chip;

wherein the memory chips have a depth of S/2 words that are accessible using the address inputs, and a width of W bits per word, wherein S and W are whole numbers and S is at least 220;

wherein at least one of the memory chips is a downgraded memory chip that has a native depth of S words that are all accessible through pins of the downgraded memory chip when not soldered to the substrate, but only S/2 words are accessible through the contact pads; and

first jumper means, mounted on the substrate, for connecting a dividing address pin of the downgraded memory chip to a fixed high voltage supply when the S/2 words are an upper half of the S words in the downgraded memory chip for an upper-half configuration, and for connecting the dividing address pin of the downgraded memory chip to a fixed low voltage supply when the S/2 words are a lower half of the S words in the downgraded memory chip for a lower-half configuration,

whereby only half of the native depth of S words of the downgraded memory chip are accessible through the contact pads of the downgraded memory module.



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Forward References: Show 4 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (4)   |   Backward references (16)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 10pp US4992984  1991-02 Busch et al.  International Business Machines Corporation Memory module utilizing partially defective memory chips
Buy PDF- 15pp US5668763  1997-09 Fujioka et al.  Fujitsu Limited Semiconductor memory for increasing the number of half good memories by selecting and using good memory blocks
Buy PDF- 15pp US5691945  1997-11 Liou et al.  Macronix International Co., Ltd. Technique for reconfiguring a high density memory
Buy PDF- 23pp US5758056  1998-05 Barr   Memory system having defective address identification and replacement
Buy PDF- 8pp US5841957  1998-11 Ju et al.  Acti Technology Corp. Programmable I/O remapper for partially defective memory devices
Buy PDF- 22pp US5996096  1999-11 Dell et al.  International Business Machines Corporation Dynamic redundancy for random access memory assemblies
Buy PDF- 7pp US6052798  2000-04 Jeddeloh  Micron Electronics, Inc. System and method for remapping defective memory locations
Buy PDF- 29pp US6112285  2000-08 Ganapathy et al.  Silicon Graphics, Inc. Method, system and computer program product for virtual memory support for managing translation look aside buffers with multiple page size support
Buy PDF- 59pp US6119049  2000-09 Peddle  Tandon Associates, Inc. Memory module assembly using partially defective chips
Buy PDF- 8pp US6212648  2001-01 Abe  NEC Corporation Memory module having random access memories with defective addresses
Buy PDF- 11pp US6636447  2003-10 Beer  Infineon Technologies AG Memory module, method for activating a memory cell, and method for repairing a defective memory cell
Buy PDF- 12pp US6754117  2004-06 Jeddeloh  Micron Technology, Inc. System and method for self-testing and repair of memory modules
Buy PDF- 20pp US20040088614A1  2004-05 Wu   Management system for defective memory
Buy PDF- 24pp US20060023482A1  2006-02 Dreps et al.   276-Pin buffered memory module with enhanced fault tolerance
Buy PDF- 22pp US20060036827A1  2006-02 Dell et al.   System, method and storage medium for providing segment level sparing
Buy PDF- 18pp US20060039210A1  2006-02 Blodgett   Memory address repair without enable fuses
       
Foreign References: None

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