a design scanner, receiving a textual design file specifying functions to be performed by a chip being designed, for locating domain-crossing signals generated by a first clock and sampled by a second clock, wherein the first clock and the second clock are asynchronous;

wherein the first clock has a first clock period and the second clock has a second clock period that differs from the first clock period;

a delay randomizer that randomly selects as a random delay either a first delay value or a second delay value, the first and second delay values differing by the second clock period;

wherein the delay randomizer multiplies a random binary number by a period of the second clock to generate the random delay; and

a delay applicator, coupled to the delay randomizer, for applying the random delay to a first flip-flop, the first flip-flop being clocked by the second clock and receiving one of the domain-crossing signals generated by the first clock as an input;

a simulator that simulates the textual design file using the random delays applied by the delay applicator to simulate logic hazards caused by domain-crossing signals;

a reporter for reporting machine-generated results of the simulator to a user on a display or in a machine-generated report;

wherein the delay applicator applies a series of random delays generated by the delay randomizer to a plurality of the domain-crossing signals located by the design scanner,