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 Title: |
US7308523:
Flow-splitting and buffering PCI express switch to reduce head-of-line blocking
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
Ngai, Henry P.; Coto De Caza, CA, United States of America
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| Assignee: |
Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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| Published / Filed: |
2007-12-11
/ 2006-04-10
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| Application Number: |
US2006000308597
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| IPC Code: |
Advanced:
G06F 13/00;
Core:
more...
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| ECLA Code: |
G06F13/42S;
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| U.S. Class: |
710/313;
710/316;
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| Field of Search: |
710/052-54,310,313,316
370/229,363
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| Priority Number: |
| 2006-04-10 |
US2006000308597 |
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| Abstract: |
An enhanced Peripheral Component Interconnect Express (PCIe) switch eliminates or reduces head-of-line blocking for memory reads initiated by peripheral endpoint devices. A memory-read request packet from a first peripheral endpoint device is intercepted by the enhanced PCIe switch, which generates a series of substitute request packets to the root complex and memory. The same requestor ID is used in all packets, but the original tag is replaced with a sequence of substitute tags in the substitute packets. The switch receives a sequence of reply packets with memory-read data, replaces substitute tags with original tags, and sends the reply packets to the peripheral endpoint device. Substitute request packets for different peripheral endpoint devices are alternately sent from the switch to the root complex to prevent head-of-line blocking by one peripheral endpoint device. The amount of data in each substitute request packet is smaller than the original requests to reduce blocking latencies.
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| Attorney, Agent or Firm: |
g Patent LLC ;
Auvinen, Stuart T. ;
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| Primary / Asst. Examiners: |
Auve, Glenn A.;
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| INPADOC Legal Status: |
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| Family: |
None
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First Claim:
Show all 20 claims |
1. An enhanced switch with reduced head-of-line blocking comprising: an uplink port for sending substitute request packets toward a root complex and for receiving substitute reply packets from the root complex, the substitute reply packets containing reply data read from a memory in response to the substitute request packets; a plurality of downlink ports for connecting to a plurality of peripheral endpoint devices, each downlink port for receiving original request packets from a peripheral endpoint device with a request to read the memory through the root complex, each downlink port also for receiving altered reply packets containing reply data read from the memory in response to the request; and a multiple packet generator that generates a plurality of substitute request packets from an original request packet, each substitute request packet containing a request to read a subset of data requested by the original request packet, whereby head-of-line blocking between first and second peripheral endpoint devices is reduced.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
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| Forward References: |
Show 2 U.S. patent(s) that reference this one
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