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 Title: |
US7312734:
Calibratable analog-to-digital converter system
[ Derwent Title ]
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| Country: |
US United States of America
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| Inventor: |
McNeill, John A.; Stow, MA, United States of America
Coln, Michael C.; Lexington, MA, United States of America
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| Assignee: |
Analog Devices, Inc., Norwood, MA, United States of America
other patents from ANALOG DEVICES, INC. (28725) (approx. 876)
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| Published / Filed: |
2007-12-25
/ 2006-02-06
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| Application Number: |
US2006000349400
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| IPC Code: |
Advanced:
H03M 1/12;
Core:
more...
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| ECLA Code: |
H03M1/10A; T03M1/06M7S;
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| U.S. Class: |
341/120;
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| Field of Search: |
341/118,120
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| Priority Number: |
| 2006-02-06 |
US2006000349400 |
| 2005-02-07 |
US2005000650658P |
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| Abstract: |
A calibratable analog-to-digital converter system with a split analog-to-digital converter architecture including N Analog-to-Digital Converters (ADCs) each configured to convert the same analog input signal into a digital signal. Calibration logic is responsive to the digital signals output by the N ADCs and is configured to calibrate each of the ADCs based on the digital signals output by each ADC.
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| Attorney, Agent or Firm: |
Iandiorio & Teska ;
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| Primary / Asst. Examiners: |
Williams, Howard L.;
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| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
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| Parent Case: |
RELATED APPLICATIONS
This application claims benefit of U.S. Provisional Application No. 60/650,658, filed Feb. 7, 2005, entitled “Calibratable Analog-to-Digital Converter System”.
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| Family: |
Show 2 known family members
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First Claim:
Show all 33 claims |
1. A calibratable analog-to-digital converter system comprising: a split analog-to-digital converter architecture including N Analog-to-Digital Converters (ADCs) each configured to convert the same analog input signal into a digital signal; and calibration logic, responsive to the digital signals output by the N ADCs, and configured to calibrate each of the ADCs based on the digital signals output by each ADC.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
Show description
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| Foreign References: |
None
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| Other References: |
Morin et al., An Intellectual Property Module for Auto Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters, IEEE, Proceedings. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, Jul. 19-21, 2004, pp. 111-114.
Dyer et al., A Comparison of Monolithic Background Calibration in Two Time-Interleaved Analog-to-Digital Converters, IEEE, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS '98. May 31-Jun 3, 1998, pp. 13-16 vol. 1.□□.
H. Liu et al., “A 15b 20MS/s CMOS Pipelined ADC with Digital Background Calibration,” ISSCC Dig. Tech. Papers, pp. 454-455, Feb. 2004.
K. Nair and R. Harjani, “A 96dB SFDR 50MS/s Digitally Enhanced CMOS Pipelined A/D Converter,” ISSCC Dig. Tech. Papers, pp. 456-457, Feb. 2004.
S. Ryu et al., “A 14b-Linear Capacitor Self-Trimming Pipelined ADC,” ISSCC Dig. Tech. Papers, pp. 464-465, Feb. 2004.
H.-S. Lee, “A 12-b 600 ks/s Digitally Self-Calibrated Pipelined Algorithmic ADC,” IEEE J. Solid-State Circuits, vol. 29, No. 4, pp. 509-515, Apr. 1994.
(7 pages)
Cited by 6 patents
[ISI abstract]
J. McNeill, M. Coln, and B. Larivee, “‘Split-ADC’ Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC,” ISSCC Dig. Tech. Papers, Feb. 2005.
J. McNeill, M. Coln, and B. Larivee, “‘Split-ADC’ Architecture for Deterministic Digital Background Calibration of a 16b 1MS/s ADC,” IEEE J. Solid-State Circuits, vol. 40, No. 12, pp. 2437-2445, Dec. 2005.
(9 pages)
[ISI abstract]
Karanicolas et al., “A 15-b 1MSample/s Digitally Self-Calibrated Pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, No. 12, pp. 1207-1215, Dec. 1993.
(9 pages)
Cited by 6 patents
[ISI abstract]
O. E. Erdogan, P.J. Hurst, and S. H. Lewis, “A 12-b Digital-Background-Calibrated Algorithmic ADC With -90-dB THD,” IEEE J. Solid-State Circuits, vol. 34, No. 12, pp. 1812-1820, Dec. 1999.
(9 pages)
Cited by 4 patents
[ISI abstract]
Y. Chiu; C. W. Tsang, B. Nikolic, and P. R. Gray, “Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters,” IEEE Trans. Circuits and Systems I, vol. 51, No. 1, pp. 38-46, Jan. 2004.
(9 pages)
Cited by 3 patents
[ISI abstract]
Y. Chiu, “A 1.8V 14b 10MS/s Pipelined ADC in 0.18μm CMOS with 99dB SFDR,” ISSCC Dig. Tech. Papers, pp. 458-459, Feb. 2004.
J. Li, G. Ahn, D. Chang, and U. Moon, “0.9V 12mW 2MSps Algorithmic ADC with 81dB SFDR,” VLSI Symposium Dig. Tech. Papers, pp. 436-439, 2004.
J. Li and U. Moon, “Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy,” IEEE Trans. Circuits and Systems II, vol. 50, No. 9, pp. 531-538, Sep. 2003.
(8 pages)
[ISI abstract]
I. Galton, “Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters,” IEEE Transactions on Circcuits and Systems-II: Analog and Digital Signal Processing, vol. 47, No. 3, pp. 185-196, Mar. 2000.
(12 pages)
Cited by 5 patents
[ISI abstract]
B. Murmann and B. E. Boser, “A 12b 75MS/s Pipelined ADC using Open-Loop Residue Amplification,” ISSCC Dig. Tech. Papers, pp. 328-329, Feb. 2003.
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| Continuity Data: |
| Application Number | Filed | Notes |
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US2006000349400 | 2006-02-06 | is a
related to the prior publication |
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US20060176197A1 issued 2006-08-10 Calibratable analog-to-digital converter system
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US2006000349400 | 2006-02-06 | is a
non-provisional of provisional |
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US2005000650658P
| 2005-02-07 |
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