1. A system chip with an on-chip logic analyzer integrated onto the system chip comprising: a plurality of local functional blocks that perform functions for the system chip;
a local selector, in each local functional block, the local selector outputting sampled signals that are selected from internal nodes within a local functional block;
a selection control register that controls the local selector;
a trigger comparator that receives the sampled signals from the plurality of local functional blocks and compares the sampled signals to a trigger value to determine when a trigger occurs;
a trigger state machine that enters a triggered state when the trigger occurs; and
a capture buffer that stores the sampled signals when the trigger occurs;
wherein the sampled signals are readable from the capture buffer for external analysis;
whereby internal nodes from the plurality of local functional blocks are selected for storage in the capture buffer when the trigger occurs;
wherein the trigger state machine comprises multiple levels of sub-state-machines;
wherein the trigger comparator compares multiple trigger values to the sampled signals, wherein different trigger values are compared by the trigger comparator for the multiple levels of the trigger state machine;
wherein the trigger state machine is multi-level and multi-triggered.
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