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Title: US7336283: Efficient hardware A-buffer using three-dimensional allocation of fragment memory
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Country: US United States of America

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42 pages

 
Inventor: McCormack, Joel James; Boulder, CO, United States of America
Jouppi, Norman P.; Palo Alto, CA, United States of America
Seiler, Larry Dean; Boylston, MA, United States of America

Assignee: Hewlett-Packard Development Company, L.P., Houston, TX, United States of America
other patents from HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (815532) (approx. 1,981)
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Published / Filed: 2008-02-26 / 2002-10-24

Application Number: US2002000280721

IPC Code: Advanced: G06F 12/02; G06T 1/60; G09G 5/36; G09G 5/39;
Core: more...

ECLA Code: G09G5/36C; G06F12/02C; G06F12/02D2; G06T1/60; G09G5/39;

U.S. Class: 345/543; 345/544;

Field of Search: 345/544,611,543 711/153,170-173

Priority Number:
2002-10-24  US2002000280721

Abstract:     A method and apparatus for arranging fragments in a graphics memory. Each pixel of a display has a corresponding list of fragments in the graphics memory. Each fragment describes a three-dimensional surface at a plurality of sample points associated with the pixel. A predetermined number of fragments are statically allocated to each pixel. Additional space for fragment data is dynamically allocated and deallocated. Each dynamically allocated unit of memory contains fragment data for a plurality of pixels. Fragment data are arranged to exploit modern DRAM capabilities by increasing locality of reference within a single DRAM page, by putting other fragments likely to be referenced soon in pages that belong to non-conflicting banks, and by maintaining bookkeeping structures that allow the relevant DRAM precharge and row activate operations to be scheduled far in advance of access to fragment data.

Primary / Asst. Examiners: Harrison, Chante;

Maintenance Status: CC Certificate of Correction issued
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First Claim:
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    1. A method, comprising:

statically allocating a portion of a memory to store a first pre-determined number of base fragments for each of a plurality of pixels;

storing base fragments in the statically allocated portion of memory;

dynamically allocating a portion of the memory for overflow panes of additional fragment storage, wherein the overflow panes each include storage for a second pre-determined number of fragments for each of a group of the pixels that are physically near each other in a coordinate system;

storing overflow panes in the dynamically allocated portion of memory;

maintaining address information of the overflow panes separately from fragment data comprising storing the address information in at least one array, each entry of which is associated with a group of the pixels and a group of fragments, each entry of the at least one array storing one of the addresses or a NULL value wherein the at least one array is indexed by at least part of the coordinates of the pixels and by a value representative of at least part of a fragment number;

retrieving the overflow panes from the dynamically allocated portion of memory using the maintained address information for rendering an image; and

rendering the image on a display.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (4)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 24pp US6204859  2001-03 Jouppi et al.  Digital Equipment Corporation Method and apparatus for compositing colors of images with memory constraints for storing pixel data
Buy PDF- 21pp US6704026  2004-03 Kurihara et al.  Sun Microsystems, Inc. Graphics fragment merging for improving pixel write bandwidth
Buy PDF- 13pp US6965980  2005-11 Champion  Sony Corporation Multi-sequence burst accessing for SDRAM
Buy PDF- 72pp US20050231526A1  2005-10 MacInnis et al.   Graphics display system with anti-aliased text and graphics feature
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

US2002000280721 2002-10-24  is a related to the prior publication
     US20040080512A1 issued 2004-04-29  Efficient hardware a-buffer using three-dimensional allocation of fragment memory


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