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Title: US7337339: Multi-level power monitoring, filtering and throttling at local blocks and globally
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Country: US United States of America

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Inventor: Choquette, Jack H.; Mountain View, CA, United States of America
Normoyle, Kevin B.; Santa Clara, CA, United States of America
Atmeh, Elias; San Jose, CA, United States of America
Sellers, Scott D.; Menlo Park, CA, United States of America
Sundaresan, Murali; Sunnyvale, CA, United States of America
Gautho, Manuel; Los Gatos, CA, United States of America

Assignee: Azul Systems, Inc., Mountain View, CA, United States of America
other patents from AZUL SYSTEMS, INC. (874053) (approx. 2)
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Published / Filed: 2008-02-26 / 2005-09-15

Application Number: US2005000162578

IPC Code: Advanced: G06F 1/26; G06F 1/32;
Core: more...

ECLA Code: G06F1/32P;

U.S. Class: 713/320; 713/300;

Field of Search: 713/300,320

Priority Number:
2005-09-15  US2005000162578

Abstract:     Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controllers. When a local block executes an instruction or accesses memory, an event is generated and looked up in a local power estimate table. A local power estimate for that event is sent to the global power manager, which sums all local power estimates received from all local blocks. An exponential moving average (EMA) is generated and compared to a global power threshold. When global power is over the threshold, local targets are sent to power managers that generate and monitor local power averages that must remain under the local target. The local block is throttled by the local power manager to reduce power when the local target is exceeded.

Attorney, Agent or Firm: Auvinen, Stuart I. ; gPatent LLC ;

Primary / Asst. Examiners: Cao, Chun; Abbaszadeh, Jaweed A

Family: None

First Claim:
Show all 17 claims
    1. A global-monitoring and local-throttling power manager comprising:

a plurality of local blocks that generate events as power is consumed;

a plurality of local power tables that have event entries storing local power estimates for the events;

a plurality of local power managers, each coupled to a local power table in the plurality of local power tables, for generating a local power estimate in response to an event from a local block that is power-controlled by the local power manager;

a global power summer that receives the local power estimates from the plurality of local power managers and generates a global power estimate as a sum of the plurality of local power estimates for the plurality of local blocks;

a global power filter, receiving the global power estimate from the global power summer, for generating a filtered global power estimate;

a global power table that stores a global power threshold;

a global comparator for comparing the filtered global power estimate to the global power threshold from the global power table and enabling a throttling mode when the filtered global power estimate exceeds the global power threshold;

the plurality of local power managers being enabled to reduce power consumption of the plurality of local blocks in response to enabling of the throttling mode by the global comparator;

wherein each local power manager comprises:

a local power target table that stores a local power target;

a local filter that receives the local power estimate read from the local power table and generates a filtered local power estimate; and

a local comparator that compares the filtered local power estimate to the local power target from the local power target table and enables a reduced-power mode of the local block when the filtered local power estimate exceeds the local power target;

whereby each local power manager causes its local block to reduce power consumption in response to enabling of the throttling mode by the global comparator and the filtered local power estimate exceeding the local power target and whereby power is estimated and reduced locally and monitored globally.



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Forward References: Show 3 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (3)   |   Backward references (28)   |   Citation Link

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PDF
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Foreign References: None

Other References:
  • Intel Corp. “Intel 820 Chipset Family: 82820 Memory Controller Hub (MCH) Datasheet”, pp. 1-6, 11-17, 128-136, Jul. 2000.
  • J. Wei, “Foxton Technology Pushes Processor Frequency, Application Performance”, Technology@Intel Magazine, pp. 1-5, Sep. 2005.


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