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Title: US7363417: Optimized topographies for dynamic allocation of PCI express lanes using differential muxes to additional lanes to a host
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Country: US United States of America

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18 pages

 
Inventor: Ngai, Henry P.; Coto De Caza, CA, United States of America

Assignee: Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: 2008-04-22 / 2005-08-09

Application Number: US2005000161612

IPC Code: Advanced: G06F 13/00;

U.S. Class: 710/316; 710/317; 710/305; 710/307;

Field of Search: 710/300-317,62-64,72,8-19,104-105

Abstract:     Many Peripheral Component Interconnect Express (PCIE) lanes are available between a root complex host and peripherals inserted into slots. Each PCIE lane is a bi-directional serial bus, with a transmit differential pair and a receive differential pair of data lines. Some lanes are directly connected from the root complex host to each slot. Each slot is driven by a different port and a different direct physical layer on the host. Other lanes are configurable and can be driven by any port and use a configurable physical layer on the host. These configurable lanes pass through an external switch or crossbar that connects the lanes from the host to one or more of the slots. The direct-connect lanes can be the first lanes to a slot while the configurable lanes are the higher-numbered lanes.

Attorney, Agent or Firm: gPatent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Phan, Raymond N;

       
Related Applications:
Application Number Filed Patent Pub. Date  Title
US2004000904880 2004-12-02    2007-02-06  Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host


       
Parent Case: RELATED APPLICATION
    This application is a continuation-in-part of the application for “Dynamic Allocation of PCI Express Lanes Using a Differential Mux to an Additional Lane to a Host”, U.S. Ser. No. 10/904,880, filed Dec. 2, 2004 now U.S. Pat. No. 7,174,411.

Family: None

First Claim:
Show all 19 claims
    1. A re-configurable bus system comprising:

a host interface to a host;

a physical-layer switch;

a first slot for receiving a first peripheral device;

a second slot for receiving a second peripheral device;

a first direct lane between the host interface and the first slot;

a second direct lane between the host interface and the second slot;

configurable lanes between the host interface and the physical-layer switch;

wherein each of the first direct lane, the second direct lane, and the configurable lanes is a bi-directional serial bus;

first configurable lanes between the physical-layer switch and the first slot; and

second configurable lanes between the physical-layer switch and the second slot;

wherein the physical-layer switch can be configured into a first configuration wherein the configurable lanes connect to the first configurable lanes to the first slot, the first direct lane connects to the first slot, and the second direct lane connects to the second slot;

wherein the physical-layer switch can be configured into a second configuration wherein the configurable lanes connect to the second configurable lanes to the second slot, the second direct lane connects to the second slot, and the first direct lane connects to the first slot.



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Forward References: Show 1 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (1)   |   Backward references (9)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 23pp US4490788  1984-12 Rasmussen  Schlumberger Technology Corporation Well-logging data processing system having segmented serial processor-to-peripheral data links
Buy PDF- 18pp US5144293  1992-09 Rouse  International Business Machines Corporation Serial link communication system with cascaded switches
Buy PDF- 19pp US5613141  1997-03 Szatkowski et al.  International Business Machines Corporation Data storage subsystem having dedicated links connecting a host adapter, controller and direct access storage devices
Buy PDF- 9pp US5974058  1999-10 Burns et al.  Storage Technology Corporation System and method for multiplexing serial links
Buy PDF- 9pp US6154797  2000-11 Burns et al.  Storage Technology Corporation System and method for multiplexing serial links
Buy PDF- 10pp US6301637  2001-10 Krull et al.  Storage Technology Corporation High performance data paths
Buy PDF- 30pp US6556628  2003-04 Poulton et al.  The University of North Carolina at Chapel Hill Methods and systems for transmitting and receiving differential signals over a plurality of conductors
Buy PDF- 9pp US6754757  2004-06 Lewis  Turin Networks Full mesh interconnect backplane architecture
Buy PDF- 18pp US7174411  2007-02 Ngai  Pericom Semiconductor Corp. Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

11161612   is a continuation in part of
US2004000904880  2004-12-02
     US7174411 issued 2007-02-06   Dynamic allocation of PCI express lanes using a differential mux to an additional lane to a host


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