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 Title: |
US7366843:
Computer system implementing synchronized broadcast using timestamps
[ Derwent Title ]
>> View Certificate of Correction for this publication
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| Country: |
US United States of America
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| Inventor: |
Cypher, Robert E.; Saratoga, CA, United States of America
Wood, David A.; Madison, WA, United States of America
Hill, Mark D.; Madison, WI, United States of America
Wicki, Thomas M.; Palo Alto, CA, United States of America
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| Assignee: |
Sun Microsystems, Inc., Santa Clara, CA, United States of America
other patents from SUN MICROSYSTEMS, INC. (551495) (approx. 3,879)
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| Published / Filed: |
2008-04-29
/ 2003-06-30
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| Application Number: |
US2003000610009
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| IPC Code: |
Advanced:
G06F 3/00;
G06F 12/08;
G06F 13/18;
Core:
G06F 13/16;
more...
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| ECLA Code: |
G06F12/08B4P;
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| U.S. Class: |
Current:
711/141;
710/001;
710/004;
710/036;
710/052;
711/167;
711/E12.026;
Original:
711/141;
711/141;
711/167;
710/004;
710/036;
710/052;
710/001;
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| Field of Search: |
711/141,167
710/004,36,52,1
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| Priority Number: |
| 2003-06-30 |
US2003000610009 |
| 2002-06-28 |
US2002000392178P |
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| Abstract: |
A computer system may include a system memory, an active device configured to access data stored in the system memory, where the active device includes a cache configured to store data accessed by the active device, an address network for conveying address packets between the active device and the system memory, and a data network for conveying data packets between the active device and the system memory. An access right corresponding to a given block allocated in the cache transitions in response to a corresponding data packet being received by the cache. An ownership responsibility for the given block transitions in response to a corresponding address packet being received by the cache. The access right transitions at a different time than the ownership responsibility transitions. The cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet.
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| Attorney, Agent or Firm: |
Meyertons Hood Kivlin Kowert & Goetzel, P.C. ;
Kivlin, B. Noël ;
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| Primary / Asst. Examiners: |
Portka, Gary; Choe, Yong J
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| Maintenance Status: |
CC Certificate of Correction issued
View Certificate of Correction
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| INPADOC Legal Status: |
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Family Legal Status Report
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| Family: |
Show 2 known family members
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First Claim:
Show all 20 claims |
1. A computer system comprising: a system memory; a first active device configured to access data stored in the system memory, wherein the first active device includes a first cache configured to store data accessed by the first active device; an address network for conveying address packets between the first active device and the system memory; a data network for conveying data packets between the first active device and the system memory; a second active device including a second cache; wherein the first cache is configured to transition an access right corresponding to a given block allocated in the first cache in response to a corresponding data packet being received by the first cache; wherein the first cache is configured to transition an ownership responsibility for the given block allocated in the first cache in response to a corresponding address packet being received by the first cache, wherein the first cache is configured to transition the access right at a different time than the ownership responsibility transitions; wherein the first cache is configured to inhibit receipt of the corresponding data packet based on a value of a timestamp associated with the corresponding data packet; and wherein the second active device is configured to assign the timestamp to the corresponding data packet and to send the timestamp and the corresponding data packet on the data network to the first active device.
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| Background / Summary: |
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| Drawing Descriptions: |
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| Description: |
Show description
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| Foreign References: |
None
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| Other References: |
“Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol”, Sorin, et al, IEEE Transactions on Parallel and Distributed Systems, vol. 13, No. 6, Jun. 2002, http://www.cs.wisc.edu/multifacet/papers/tpds02—lamport.pdf.
“Multicast Snooping: A New Coherence Method Using a Multicast Address Network”, Bilir, et al, The 26th International Symposium on Computer Architecture, IEEE, Atlanta, GA, May 2-4, 1999, http://csdl.computer.org/comp/proceedings/isca/1999/0170/00/01700294abs.htm.
“Architecture and Design of AlphaServer GS320”, Gharachorloo, et al, ACM Sigplan Notices, vol. 35, Issue 11, Nov. 2000, http://portal.acm.org/citation.cfm?id=356991&dl=ACM&coll=portal.
“View Caching: Efficient Software Shared Memory for Dynamic Computations”, Karamcheti, et al, 11th International Parallel Processing Symposium, Geneva, Switzerland, Apr. 1-5, 1997, http://ipdps.eece.unm.edu/1997/s13/318.pdf.
“Cache-Coherent Distributed Shared Memory: Perspectives on Its Development and Future Challenges”, Hennessy, et al, Proceedings of the IEEE, vol. 87, Issue 3, Mar. 1999, ISSN 0018-9219, http://cva.stanford.edu/cs99s/papers/hennessy-cc.pdf.
“A Survey of Cache Coherence Mechanisms in Shared Memory Multiprocessors”, Lawrence, Department of Computer Science, University of Manitoba, Manitoba, Canada, May 14, 1998, http://www.cs.uiowa.edu/˜rlawrenc/research/Papers/cc.pdf.
“Bandwidth Adaptive Snooping”, Martin, et al. 8th Annual International Symposium on High-Performance Computer Architecture (HPCA-8), Cambridge, MA, Feb. 2-6, 2002.
“Timestamp Snooping: An Approach for Extending SMPs”, Martin, et al., 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX), Cambridge, MA, Nov. 13-15, 2000.
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| Continuity Data: |
| Application Number | Filed | Notes |
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US2003000610009 | 2003-06-30 | is a
related to the prior publication |
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US20040024925A1 issued 2004-02-05 Computer system implementing synchronized broadcast using timestamps
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US2003000610009 | 2003-06-30 | is a
non-provisional of provisional |
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US2002000392178P
| 2002-06-28 |
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