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Title: US7366847: Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag
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Country: US United States of America

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24 pages

 
Inventor: Kruckemyer, David A.; Vancouver, Canada
Normoyle, Kevin B.; Santa Clara, CA, United States of America
Hathaway, Robert G.; Sunnyvale, CA, United States of America

Assignee: Azul Systems, Inc., Mountain View, CA, United States of America
other patents from AZUL SYSTEMS, INC. (874053) (approx. 2)
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Published / Filed: 2008-04-29 / 2006-02-06

Application Number: US2006000307413

IPC Code: Advanced: G06F 12/00;
Core: more...

ECLA Code: G06F12/08B4P2A; G06F12/08B4P2R;

U.S. Class: 711/144; 711/141;

Field of Search: Non/00e

Priority Number:
2006-02-06  US2006000307413

Abstract:     A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidations. The central coherency controller reads snoop tags to identify sharing caches having a copy of a requested cache line. The central coherency controller sends an ordering message to the requesting filter pipe. The ordering message has an invalidate count indicating the number of sharing caches. Each sharing cache receives an invalidation message from the central coherency controller, invalidates its copy of the cache line, and sends an invalidation acknowledgement message to the requesting filter pipe. The requesting filter pipe decrements the invalidate count until all sharing caches have acknowledged invalidation. All ordering, data, and invalidation acknowledgement messages must be received by the requesting filter pipe before loading the data into its cache.

Attorney, Agent or Firm: g Patent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Kim, Hong; Dinh, Ngoc

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Parent Case: RELATED APPLICATION
    This application is related to the application for “Duplicate Snoop Tags Partitioned Across Multiple Processor/Cache Chips in a Multi-Processor System”, U.S. Ser. No. 10/711,387, now U.S. Pat. No. 7,225,300 filed Sep. 15, 2004.

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First Claim:
Show all 20 claims
    1. A distributed coherency processor comprising:

a plurality of filter pipes for tracking memory requests from a plurality of caches, a requesting filter pipe in the plurality of filter pipes storing a memory-request entry having a request address for a requested cache line;

a central coherency controller that receives memory requests from the plurality of filter pipes, the central coherency controller generating ordering messages and invalidate messages in response to the memory requests;

a snoop tag directory storing snoop entries that indicate sharing caches having a copy of the requested cache line at the request address;

the central coherency controller further for searching the snoop tag directory using the request address from a memory request from a requesting cache, and for sending invalidate messages to sharing filter pipes for the sharing caches identified by the snoop tag directory;

an ordering message sent from the central coherency controller to the requesting filter pipe, the ordering message indicating an order for processing memory requests, the order determined by the central coherency controller;

an invalidate count in the ordering message, the invalidate count indicating a number of the sharing caches in the plurality of caches for the sharing caches identified by the snoop tag directory; and

a plurality of invalidate acknowledgement messages, generated by the sharing caches in response to the invalidate messages from the central coherency controller, each of the invalidate acknowledgement messages verifying invalidation of the copy of the requested cache line by the sharing cache;

wherein the requesting filter pipe receives the plurality of invalidate acknowledgement messages and releases data in the requested cache line for processing after a number of the plurality of invalidate acknowledgement messages received by the requesting filter pipe matches the invalidate count from the ordering message,

whereby coherency order is determined by the central coherency controller and coherency tracking is performed by the requesting filter pipe in the plurality of filter pipes.



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Forward References: Show 2 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (2)   |   Backward references (13)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 15pp US4463420  1984-07 Fletcher  International Business Machines Corporation Multiprocessor cache replacement under task control
Buy PDF- 49pp US5623628  1997-04 Brayton et al.  Intel Corporation Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue
Buy PDF- 21pp US5778434  1998-07 Nguyen et al.  Seiko Epson Corporation System and method for processing multiple requests and out of order returns
Buy PDF- 25pp US6173370  2001-01 Tanioka  NEC Corporation Cache system capable of keeping cache-coherency among store-in-caches of two central processing units on occurrence of store-confliction
Buy PDF- 15pp US6321305  2001-11 Arimilli et al.  International Business Machines Corporation Multiprocessor system bus with combined snoop responses explicitly cancelling master allocation of read data
Buy PDF- 15pp US6347361  2002-02 Arimilli et al.  International Business Machines Corporation Cache coherency protocols with posted operations
Buy PDF- 16pp US6463507  2002-10 Arimilli et al.  International Business Machines Corporation Layered local cache with lower level cache updating upper and lower level cache directories
Buy PDF- 16pp US6502171  2002-12 Arimilli et al.  International Business Machines Corporation Multiprocessor system bus with combined snoop responses explicitly informing snoopers to scarf data
Buy PDF- 41pp US6636949  2003-10 Barroso et al.  Hewlett-Packard Development Company, L.P. System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing
Buy PDF- 12pp US6654858  2003-11 Asher et al.  Hewlett-Packard Development Company, L.P. Method for reducing directory writes and latency in a high performance, directory-based, coherency protocol
Buy PDF- 15pp US6701416  2004-03 Arimilli et al.  International Business Machines Corporation Cache coherency protocol with tagged intervention of modified values
Buy PDF- 12pp US20030120877A1  2003-06 Jahnke   Embedded symmetric multiprocessor system
Buy PDF- 12pp US20040003184A1  2004-01 Safranek et al.   Partially inclusive snoop filter
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

US2006000307413 2006-02-06  is a related to the prior publication
     US20070186054A1 issued 2007-08-09  Distributed Cache Coherence at Scalable Requestor Filter Pipes that Accumulate Invalidation Acknowledgements from other Requestor Filter Pipes Using Ordering Messages from Central Snoop Tag


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