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Title: US7389381: Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules
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Country: US United States of America

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20 pages

 
Inventor: Co, Ramon S.; Trabuco Canyon, CA, United States of America 92679

Assignee: None

Published / Filed: 2008-06-17 / 2006-04-05

Application Number: US2006000308545

IPC Code: Advanced: G06F 13/28;
Core: G06F 13/20;

ECLA Code: G06F13/16D6; G06F13/16D2;

U.S. Class: 711/115; 711/154;

Field of Search: 711/115,154,5 710/022,300,305

Priority Number:
2006-04-05  US2006000308545

Abstract:     A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB.

Attorney, Agent or Firm: gPatent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Le, Vu A;

INPADOC Legal Status: None          Buy Now: Family Legal Status Report

Parent Case: RELATED APPLICATION
    This application is related to the co-pending application for “Branching Fully-Buffered Memory-Module with Two Downlink and One Uplink Ports”, U.S. Ser. No. 11/306,481, filed Dec. 29, 2005.

Family: Show 2 known family members

First Claim:
Show all 20 claims
    1. A branching fully-buffered memory-bus module comprising:

a substrate containing wiring traces for conducting signals;

a plurality of contact pads along a first edge of the substrate, the plurality of contact pads for mating with a memory module socket on a motherboard;

a branching Advanced Memory Buffer (AMB) mounted on the substrate for buffering host data;

uplink contact pads, in the plurality of contact pads, that carry southbound uplink frames of the host data generated by the host for writing to memory chips in downstream memory modules, and that carry northbound uplink frames of host data read from memory chips in downstream memory modules toward the host;

first downlink contact pads, in the plurality of contact pads, that carry first southbound downlink frames of the host data generated by the host for writing to a first plurality of memory chips in a first downstream memory module in a first branch, and that carry first northbound downlink frames of host data read from the first plurality of memory chips in the first downstream memory module in the first branch;

second downlink contact pads, in the plurality of contact pads, that carry second southbound downlink frames of the host data generated by the host for writing to a second plurality of memory chips in a second downstream memory module in a second branch, and that carry second northbound downlink frames of host data read from the second plurality of memory chips in the second downstream memory module in the second branch;

wherein the branching AMB connects through the wiring traces to the uplink contact pads, to the first downlink contact pads, and to the second downlink contact pads;

a replicator, in the branching AMB, for copying the southbound uplink frames received from the uplink contact pads to the first downlink contact pads to generate the first southbound downlink frames, and for copying the southbound uplink frames received from the uplink contact pads to the second downlink contact pads to generate the second southbound downlink frames; and

a northbound merger, in the branching AMB, for transferring the first northbound downlink frames received from the first downlink contact pads to the uplink contact pads to generate the northbound uplink frames, and for transferring the second northbound downlink frames received from the second downlink contact pads to the uplink contact pads to generate the northbound uplink frames,

whereby the branching fully-buffered memory-bus module replicates southbound uplink frames to generate both the first southbound downlink frames to the first branch of the first downstream memory module and the second southbound downlink frames to the second branch of the second downstream memory module.



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Forward References: Show 1 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (1)   |   Backward references (13)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 18pp US6240101  2001-05 Co et al.  Kingston Technology Co. Bi-directional daisy-chain cascading of network repeaters
Buy PDF- 11pp US6317352  2001-11 Halbert et al.  Intel Corporation Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
Buy PDF- 16pp US6493250  2002-12 Halbert et al.  Intel Corporation Multi-tier point-to-point buffered memory interface
Buy PDF- 10pp US6553450  2003-04 Dodd et al.  Intel Corporation Buffer to multiply memory interface
Buy PDF- 12pp US6625687  2003-09 Halbert et al.  Intel Corporation Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
Buy PDF- 15pp US7197676  2007-03 Co et al.  Kingston Technology Corp. Loop-Back Memory-Module Extender Card for Self-Testing Fully-Buffered Memory Modules
Buy PDF- 46pp US20020101755A1  2002-08 Funaba et al.   Memory module
Buy PDF- 54pp US20020159284A1  2002-10 Funaba et al.   Memory system
Buy PDF- 103pp US20040105292A1  2004-06 Matsui   Memory system and data transmission method
Buy PDF- 52pp US20040256638A1  2004-12 Perego et al.   Configurable width buffered module having a bypass circuit
Buy PDF- 54pp US20050007805A1  2005-01 Ware et al.   Configurable width buffered module having flyby elements
Buy PDF- 59pp US20050010737A1  2005-01 Ware et al.   Configurable width buffered module having splitter elements
Buy PDF- 14pp US20050060600A1  2005-03 Jeddeloh   System and method for on-board timing margin testing of memory modules
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

12115200   is a continuation of
>US2006000308545<  2006-04-05
     US7389381 issued 2008-06-17   Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules


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