an input buffer receiving an input signal and generating a buffered input signal;

an adjustable delay circuit, receiving the buffered input signal from the input buffer, and generating a delayed input signal that is delayed by an adjustable delay width; and

a summer, coupled to the input buffer and to the adjustable delay circuit, for generating an output signal as a combination of the buffered input signal and the delayed input signal;

wherein the summer combines a first current from the input buffer with a delayed current from the adjustable delay circuit to generate a combined current as the output signal;

wherein the adjustable delay width is adjustable by a user;

wherein the adjustable delay circuit inverts polarity of the first current from the input buffer to generate the delayed current that changes polarity after the adjustable delay width from a polarity change of the first current; wherein the adjustable delay circuit does not receive a clock;

wherein data changes on a transmission line carrying the data after a bit period or after a multiple of the bit period;

wherein the adjustable delay width is adjustable to values that are less than the bit period,

whereby the adjustable delay width is less than the bit period and whereby current polarity changes are delayed by the adjustable delay circuit and inverted.