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Title: US7404041: Low complexity speculative multithreading system based on unmodified microprocessor core
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Country: US United States of America

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Inventor: Gara, Alan G.; Mount Kisco, NY, United States of America
Gschwind, Michael K.; Chappaqua, NY, United States of America
Salapura, Valentina; Chappaqua, NY, United States of America

Assignee: International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 2008-07-22 / 2006-02-10

Application Number: US2006000351830

IPC Code: Advanced: G06F 12/00;
Core: more...

ECLA Code: G06F12/08B4L; G06F9/38D; G06F9/38E2; G06F9/38E4; S06F12/08B4P;

U.S. Class: 711/121; 711/141;

Field of Search: 711/120,121,141,146 712/216

Priority Number:
2006-02-10  US2006000351830

Abstract:     A system, method and computer program product for supporting thread level speculative execution in a computing environment having multiple processing units adapted for concurrent execution of threads in speculative and non-speculative modes. Each processing unit includes a cache memory hierarchy of caches operatively connected therewith. The apparatus includes an additional cache level local to each processing unit for use only in a thread level speculation mode, each additional cache for storing speculative results and status associated with its associated processor when handling speculative threads. The additional local cache level at each processing unit are interconnected so that speculative values and control data may be forwarded between parallel executing threads. A control implementation is provided that enables speculative coherence between speculative threads executing in the computing environment.

Attorney, Agent or Firm: Scully, Scott, Murphy & Presser, P.C. ; Morris, Esq., Daniel P. ;

Primary / Asst. Examiners: Peugh, Brian R;

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Parent Case: CROSS-REFERENCE TO RELATED APPLICATIONS
    The present application is based on applicants' commonly-owned, U.S. patent application Ser. No. 11/351,829, now U.S. Pat. No. 7,350,027 filed on Feb. 10, 2006 and entitled ARCHITECTURAL SUPPORT FOR THREAD LEVEL SPECULATIVE EXECUTION, the contents and disclosure of which is incorporated by reference as if fully set forth herein.

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Claim     1. A method for implementing a thread-level speculation system on a chip multiprocessor having multiple processing units and an associated cache memory hierarchy, wherein programming threads in speculative and non-speculative modes are assigned to said multiple processing units for parallel execution, said method comprising:

providing an additional private local cache dedicated to a respective processing unit for use only in thread-level speculation mode, each said private local cache for storing speculative results and state associated with an executing thread;

providing a dedicated bus interconnecting said dedicated private local caches for enabling data forwarding between parallel executing threads to detect data dependency conditions;

receiving, at a processing unit, a thread identifier for executing a speculative or non-speculative programming thread;

starting, at said processing unit, a current thread execution in response to receiving a thread identifier;

implementing, at a processing unit, logic for performing:

identifying a start of a new speculative thread;

tracking state information including speculative memory state associated with said new speculative thread;

storing speculative memory state information associated with said new speculative thread in said dedicated local cache;

said logic further implementing one or more of:

determining whether a data dependency violation condition has occurred in one of: a current or an older, less speculative thread, and in response to a detected data dependency violation condition performing one or more of:

stopping execution of a next speculative thread; and

discarding the stored speculative memory state information associated with said current or older, less speculative thread in said dedicated local cache; and

stopping the execution of the current thread or older, less speculative thread; and,

said logic determining whether a current or older, less speculative thread has become non-speculative and performing one or more of:

committing data results of the non-speculative thread execution to a lower memory level of said cache memory hierarchy when said speculative thread becomes non-speculative; and,

initiating a new speculative thread processing request and, after executing remaining instructions in said executing non-speculative thread;

promoting a next speculative thread into a non-speculative thread; and,

restarting thread execution when a thread has been aborted in response to data dependency violation condition;

wherein said bus interconnected dedicated private local caches and implemented logic for tracking speculative access between multiple processing units enables coherent speculative multithreading without modification to a processing unit core.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (5)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 29pp US6704841  2004-03 Chaudhry et al.  Sun Microsystems, Inc. Method and apparatus for facilitating speculative stores in a multiprocessor system
Buy PDF- 12pp US7216202  2007-05 Chaudhry et al.  Sun Microsystems, Inc. Method and apparatus for supporting one or more servers on a single semiconductor chip
Buy PDF- 15pp US7269717  2007-09 Tremblay et al.  Sun Microsystems, Inc. Method for reducing lock manipulation overhead during access to critical code sections
Buy PDF- 23pp US20020046324A1  2002-04 Barroso et al.   Scalable architecture based on single-chip multiprocessing
Buy PDF- 20pp US20070192540A1  2007-08 Gara et al.   Architectural support for thread level speculative execution
       
Foreign References: None

Other References:
  • Marcuello et al., “Thread Partitioning and Value Prediction for Exploiting Speculative Thread-Level Parallelism”, © 2004 IEEE, p. 114-125.
  • Sarangi, et al., “ReSlice: Selective Re-Execution of Long-Retired Misspeculated Instructions Using Forward Slicing”, © 2005 IEEE, p. 1-12.
  • Tsai, et al., “The Superthreaded Processor Architecture”, © 1999 IEEE, p. 861-902.
  • Whaley et al., “Heuristics for Profile-driven Method-level Speculative Parallelization”, © 2005 IEEE, p. 1-10.


  • Continuity Data:
    Application Number Filed Notes

    US2006000351830 2006-02-10  is a related to the prior publication
         US20070192545A1 issued 2007-08-16  Low complexity speculative multithreading system based on unmodified microprocessor core

    12147914   is a continuation of
    >US2006000351830<  2006-02-10
         US7404041 issued 2008-07-22   Low complexity speculative multithreading system based on unmodified microprocessor core


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