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Title: US7414312: Memory-module board layout for use with memory chips of different data widths
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Country: US United States of America

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Inventor: Nguyen, Henry H. D.; Fountain Valley, CA, United States of America
Burlington, Mark; Aliso Viejo, CA, United States of America

Assignee: Kingston Technology Corp., Fountain Valley, CA, United States of America
other patents from KINGSTON TECHNOLOGY COMPANY (741845) (approx. 14)
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Published / Filed: 2008-08-19 / 2005-05-24

Application Number: US2005000908718

IPC Code: Advanced: G11C 5/06; H01L 23/34; H05K 7/00;
Core: more...

ECLA Code: G11C5/00; G11C8/12; H05K1/18B;

U.S. Class: 257/724; 257/786; 257/E23.141; 361/760; 361/784; 361/803; 365/063;

Field of Search: Non/00e

Priority Number:
2005-05-24  US2005000908718

Abstract:     A memory module substrate printed-circuit board (PCB) has multi-type footprints and an edge connector for mating with a memory module socket on a motherboard. Two or more kinds of dynamic-random-access memory (DRAM) chips with different data I/O widths can be soldered to solder pads around the multi-type footprints. When x4 DRAM chips with 4 data I/O pins are soldered over the multi-type footprints, the memory module has a rank-select signal that drives chip-select inputs to all DRAM chips. When x8 DRAM chips with 8 data I/O pins are soldered over the multi-type footprints, the memory module has two rank-select signals. One rank-select drives chip-select inputs to front-side DRAM chips while the second rank-select drives chip-select inputs to back-side DRAM chips. Wiring traces on the PCB cross-over data nibbles between the solder pads and the connector to allow two x4 chips to drive a byte driven by only one x8 chip.

Attorney, Agent or Firm: gPatent LLC ; Auvinen, Stuart J. ;

Primary / Asst. Examiners: Chambliss, Alonzo;

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First Claim:
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    1. A multi-type memory module substrate board comprising:

a substrate board, the substrate board being a multi-layer printed-circuit board (PCB) substrate;

an edge connector having connector pads for mating with metal connectors in a memory module socket on a motherboard, the connector pads including data pads;

a plurality of chip pairings on the substrate board that each drive different data groups of data pads in the edge connector, each chip pairing comprising:

a first multi-type footprint on a front side of the substrate board, the first multi-type footprint having a size to accept a first memory chip;

wherein the first memory chip has a first data width when a first type of memory module is being assembled from the multi-type memory module substrate board, and has a second data width when a second type of memory module is being assembled from the multi-type memory module substrate board;

wherein the second data width is larger than the first data width;

first solder pads surrounding the first multi-type footprint, the first solder pads for forming solder connections to metal leads of the first memory chip during assembly;

first wiring traces formed on or within the substrate board, the first wiring traces connecting a first data group of the first solder pads to a first data group of the connector pads in the edge connector;

second wiring traces formed on or within the substrate board, the second wiring traces connecting a second data group of the first solder pads to a second data group of the connector pads in the edge connector;

a second multi-type footprint on a back side of the substrate board, the second multi-type footprint having a size to accept a second memory chip;

second solder pads surrounding the second multi-type footprint, the second solder pads for forming solder connections to metal leads of the second memory chip during assembly;

first cross-over wiring traces formed on or within the substrate board, the first cross-over wiring traces connecting a first data group of the second solder pads to the second data group of the connector pads in the edge connector; and

second cross-over wiring traces formed on or within the substrate board, the second cross-over wiring traces connecting a second data group of the second solder pads to the first data group of the connector pads in the edge connector;

wherein when the first and second memory chips each have the first data width, the first memory chip drives data onto the first data group in the edge connector but does not drive data onto the second data group in the edge connector, and the second memory chip drives data onto the second data group in the edge connector but does not drive data onto the first data group of in the edge connector;

wherein when the first and second memory chips each have the second data width, the first memory chip drives data onto the first data group in the edge connector and drives data onto the second data group of in the edge connector in response to a first chip-select signal, and the second memory chip drives data onto the first data group in the edge connector and drives data onto the second data group of in the edge connector in response to a second chip-select signal;

wherein the first and second chip-select signals are activated on different access cycles for memory chips having the second data width,

whereby the multi-type memory module substrate board is assembled into the first type of memory module when the first and second memory chips have the first data width, and into the second type of memory module when the first and second memory chips have the second data width.



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Forward References: Show 1 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (1)   |   Backward references (17)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 6pp US4884237  1989-11 Mueller et al.  International Business Machines Corporation Stacked double density memory module using industry standard memory chips
Buy PDF- 14pp US5754408  1998-05 Derouiche  Mitsubishi Semiconductor America, Inc. Stackable double-density integrated circuit assemblies
Buy PDF- 14pp US6038132  2000-03 Tokunaga et al.  Mitsubishi Denki Kabushiki Kaisha Memory module
Buy PDF- 12pp US6542393  2003-04 Chu et al.  MA Laboratories, Inc. Dual-bank memory module with stacked DRAM chips having a concave-shaped re-route PCB in-between
Buy PDF- 12pp US6614664  2003-09 Lee  Samsung Electronics Co., Ltd. Memory module having series-connected printed circuit boards
Buy PDF- 16pp US6751113  2004-06 Bhakta et al.  Netlist, Inc. Arrangement of integrated circuits in a memory module
Buy PDF- 5pp US6839241  2005-01 Benisek et al.  Infineon Technologies AG Circuit module
Buy PDF- 10pp US6891729  2005-05 Ko et al.  Samsung Electronics Co., Ltd. Memory module
Buy PDF- 23pp US7224595  2007-05 Dreps et al.  International Business Machines Corporation 276-Pin buffered memory module with enhanced fault tolerance
Buy PDF- 31pp US7337522  2008-03 Engle et al.  Legacy Electronics, Inc. Method and apparatus for fabricating a circuit board with a three dimensional surface mounted array of semiconductor chips
Buy PDF- 19pp US7356737  2008-04 Cowell et al.  International Business Machines Corporation System, method and storage medium for testing a memory module
Buy PDF- 33pp US20020133665A1  2002-09 Mailloux et al.   BURST/PIPELINED EDO MEMORY DEVICE
Buy PDF- 7pp US20030067063A1  2003-04 Muff et al.   Semiconductor module having a configurable data width of an output bus, and a housing configuration having a semiconductor module
Buy PDF- 33pp US20040186956A1  2004-09 Perego et al   Configurable width buffered module
Buy PDF- 29pp US20040221106A1  2004-11 Perego et al.   Upgradable memory system with reconfigurable interconnect
Buy PDF- 52pp US20040256638A1  2004-12 Perego et al.   Configurable width buffered module having a bypass circuit
Buy PDF- 24pp US20050044302A1  2005-02 Pauley et al.   Non-standard dual in-line memory modules with more than two ranks of memory per module and multiple serial-presence-detect devices to simulate multiple modules
       
Foreign References:
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PDF
Publication Date IPC Code Assignee   Title
Buy PDF JP07022727A2 1995-01  H05K 1/18 IBIDEN CO LTD SUBSTRATE FOR MOUNTING ELECTRONIC COMPONENT 


Continuity Data:
Application Number Filed Notes

US2005000908718 2005-05-24  is a related to the prior publication
     US20060267172A1 issued 2006-11-30  Memory-Module Board Layout for Use With Memory Chips of Different Data Widths


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