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Title: US7437597: Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines
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Country: US United States of America

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Inventor: Kruckemyer, David A.; Mountain View, CA, United States of America
Normoyle, Kevin B.; Santa Clara, CA, United States of America
Choquette, Jack H.; Mountain View, CA, United States of America

Assignee: Azul Systems, Inc., Mountain View, CA, United States of America
other patents from AZUL SYSTEMS, INC. (874053) (approx. 2)
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Published / Filed: 2008-10-14 / 2005-05-18

Application Number: US2005000908586

IPC Code: Advanced: G06F 11/10;
Core: more...

ECLA Code: G06F11/10M2A1;

U.S. Class: 714/006; 714/773;

Field of Search: 714/773,774,6

Priority Number:
2005-05-18  US2005000908586

Abstract:     A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of ECC code stored is different for clean and dirty lines. Clean lines use an error-detection code that can detect longer multi-bit errors than the error correction code used by dirty lines. Dirty lines use a correction code that can correct a bit error in the dirty line, while the detection code for clean lines may not be able to correct any errors. Dirty lines' ECC is optimized for correction while clean lines' ECC is optimized for detection. A single-error-correction, double-error-detection (SECDED) code may be used for dirty lines while a triple-error-detection code is used for clean lines.

Attorney, Agent or Firm: g Patent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Baker, Stephen M.;

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 16 claims
    1. An error-correcting write-back cache comprising:

a plurality of cache lines, a cache line being selected for access by a cache hit that matches a tag portion of an address input to a store tag for the cache line;

a data field in the cache line for storing data;

an error-code field in the cache line for storing error code for the data in the cache line;

a cache-state field for the cache line, the cache-state field indicating a clean state and a dirty state, wherein the cache line in the clean state has a back-up copy of the data in an external memory, wherein the cache line in the dirty state has no back-up copy of the data in the external memory;

a syndrome generator, receiving the data from the data field and the error code from the error-code field of the cache line selected for access, the syndrome generator generating an error syndrome that indicates a detected error in the data;

an error corrector, coupled to the syndrome generator, the error corrector examining the cache-state field for the cache line to determine when the cache line is in the clean state, the error corrector re-fetching the back-up copy of the cache line from the external memory to replace the data in the data field when the syndrome generator indicates the detected error for a cache line in the clean state;

wherein the error corrector uses the error syndrome generated from the error code to locate and correct an error in the data field when the cache line is in the dirty state;

wherein the error corrector corrects single-bit errors in the data field and signals an uncorrectable error for longer multi-bit errors in the data field,

wherein single-bit errors in dirty cache lines are corrected while longer multi-bit errors are uncorrectable for dirty cache lines but corrected by re-fetching clean cache lines;

wherein the error code for dirty cache lines is a code value in a first error code, the first error code comprising a first set of error encodings of the data field;

wherein the error code for clean cache lines is a code value in a second error code, the second error code comprising a second set of error encodings of the data field,

whereby clean and dirty cache lines use different error codes in different sets of error encodings of the data field and whereby clean cache lines with detected errors are re-fetched from the external memory, and dirty cache lines are error-corrected using the error code.



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Forward References: Show 1 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (1)   |   Backward references (8)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 11pp US5233616  1993-08 Callander  Digital Equipment Corporation Write-back cache with ECC protection
Buy PDF- 14pp US5963718  1999-10 Muramatsu  NEC Corporation Method and apparatus for correcting error in control field in cache memory
Buy PDF- 8pp US6014756  2000-01 Dottling et al.  International Business Machines Corporation High availability error self-recovering shared cache for multiprocessor systems
Buy PDF- 8pp US6195729  2001-02 Arimilli et al.  International Business Machines Corporation Deallocation with cache update protocol (L2 evictions)
Buy PDF- 9pp US6408417  2002-06 Moudgal et al.  Sun Microsystems, Inc. Method and apparatus for correcting soft errors in digital data
Buy PDF- 6pp US6631489  2003-10 Quach et al.  Intel Corporation Cache memory and system with partial error detection and correction of MESI protocol
Buy PDF- 17pp US20020144061A1  2002-10 Faanes et al.   Vector and scalar data cache for a vector multiprocessor
Buy PDF- 55pp US20050022065A1  2005-01 Dixon et al.   Apparatus and method for memory with bit swapping on the fly and testing
       
Foreign References: None

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