1. A phase-change memory (PCM) comprising: a data input that receives a data word in response to a write request and a write address;
a data output that outputs a recovered data word in response to a read request and a read address;
a plurality of PCM cells each having a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase;
sense amplifiers for reading a read-codeword stored in the plurality of PCM cells in response to the read address;
write buffers for driving a write-codeword into the plurality of PCM cells in response to the write address;
an encoder, coupled between the data input and the write buffers, for generating the write-codeword from the data word;
wherein the write-codeword has fewer binary bits storable as the alloy in the amorphous state than the data word for a worst-case data word having all bits storable as the alloy in the amorphous state; and
a decoder, coupled between the sense amplifiers and the data output, for generating the recovered data word from the read-codeword,
whereby data storable as the alloy in the amorphous state is reduced for a worst-case by encoding.