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Title: US7440316: 8/9 and 8/10-bit encoding to reduce peak surge currents when writing phase-change memory
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Country: US United States of America

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18 pages

 
Inventor: Lee, Charles C.; Cupertino, CA, United States of America
Yu, Frank I-Kang; Palo Alto, CA, United States of America
Chow, David Q.; San Jose, CA, United States of America

Assignee: Super Talent Electronics, Inc, San Jose, CA, United States of America
other patents from SUPER TALENT ELECTRONICS, INC. (849512) (approx. 1)
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Published / Filed: 2008-10-21 / 2007-04-30

Application Number: US2007000741890

IPC Code: Advanced: G11C 11/00;
Core: more...

ECLA Code: G11C8/08; G11C16/02C;

U.S. Class: 365/163; 365/148;

Field of Search: 365/163

Priority Number:
2007-04-30  US2007000741890

Abstract:     Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The memory cell's reset current can be double a set current, causing peak currents to depend on write data. When all data bits are reset to the amorphous state, a very high peak current is required. To reduce this worst-case peak current, the data is encoded before storage in the PCM cells. An 8/10 encoder adds 2 bits but ensures that no more than half of the data bits are reset. An 8/9 encoder adds an indicator bit, and inverts the 8 bits to ensure that no more than half of the bits are reset. The indicator bit indicates when the 8 bit are inverted, and when the 8 bits are un-inverted. Peak currents are thus reduced by encoding to reduce reset data bits.

Attorney, Agent or Firm: gPatent LLC ; Auvinen, Stuart T. ;

Primary / Asst. Examiners: Mai, Son L;

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First Claim:
Show all 20 claims
    1. A phase-change memory (PCM) comprising:

a data input that receives a data word in response to a write request and a write address;

a data output that outputs a recovered data word in response to a read request and a read address;

a plurality of PCM cells each having a first logical state having an alloy in a crystalline phase and a second logical state having the alloy in an amorphous phase, wherein a resistance of the alloy is higher when in the amorphous phase than when in the crystalline phase;

sense amplifiers for reading a read-codeword stored in the plurality of PCM cells in response to the read address;

write buffers for driving a write-codeword into the plurality of PCM cells in response to the write address;

an encoder, coupled between the data input and the write buffers, for generating the write-codeword from the data word;

wherein the write-codeword has fewer binary bits storable as the alloy in the amorphous state than the data word for a worst-case data word having all bits storable as the alloy in the amorphous state; and

a decoder, coupled between the sense amplifiers and the data output, for generating the recovered data word from the read-codeword,

whereby data storable as the alloy in the amorphous state is reduced for a worst-case by encoding.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (18)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 16pp US5933365  1999-08 Klersy et al.  Energy Conversion Devices, Inc. Memory element with energy control mechanism
Buy PDF- 6pp US6512241  2003-01 Lai  Intel Corporation Phase change material memory device
Buy PDF- 14pp US6545907  2003-04 Lowrey et al.  Ovonyx, Inc. Technique and apparatus for performing write operations to a phase change material memory device
Buy PDF- 25pp US6768665  2004-07 Parkinson et al.  Intel Corporation Refreshing memory cells of a phase change material memory device
Buy PDF- 13pp US6869883  2005-03 Chiang et al.  Ovonyx, Inc. Forming phase change memories
Buy PDF- 11pp US7026639  2006-04 Cho et al.  Electronics and Telecommunications Research Institute Phase change memory element capable of low power operation and method of fabricating the same
Buy PDF- 23pp US7078273  2006-07 Matsuoka et al.  Hitachi, Ltd. Semiconductor memory cell and method of forming same
Buy PDF- 9pp US7103718  2006-09 Nickel et al.  Hewlett-Packard Development Company, L.P. Non-volatile memory module for use in a computer system
Buy PDF- 12pp US20030223285A1  2003-12 Khouri et al.   Single supply voltage, nonvolatile phase change memory device with cascoded column selection and simultaneous word read/write operations
Buy PDF- 18pp US20040228163A1  2004-11 Khouri et al.   Phase change memory device
Buy PDF- 16pp US20040248339A1  2004-12 Lung   High density chalcogenide memory cells
Buy PDF- 19pp US20040256610A1  2004-12 Lung   CHALCOGENIDE MEMORY DEVICE WITH MULTIPLE BITS PER CELL
Buy PDF- 12pp US20050185572A1  2005-08 Resta et al.   Fast reading, low consumption memory device and reading method thereof
Buy PDF- 20pp US20060018183A1  2006-01 De Sandre et al.   Content addressable memory cell
Buy PDF- 11pp US20060097239A1  2006-05 Hsiung   Multilevel phase-change memory, manufacture method and operating method thereof
Buy PDF- 17pp US20060126381A1  2006-06 Khouri et al.   Method of writing to a phase change memory device
Buy PDF- 30pp US20060203542A1  2006-09 Kurotsuchi et al.   Semiconductor integrated device
Buy PDF- 48pp US20060274574A1  2006-12 Choi et al.   Phase-change memory device and method of writing a phase-change memory device
       
Foreign References: None

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