requesting a schedule from a schedule cache, the schedule includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the instructions in the schedule, a list of register names used but not defined in the schedule, a list of registers defined in the schedule, and a rename map of register names for each register in the list of registers defined in the schedule, the schedule exploiting instruction-level parallelism in executing out-of-order instructions;

if the schedule is found in the schedule cache, fetching the schedule;

if the schedule is not found in the schedule cache, creating the schedule;

renaming the registers in the schedule to avoid false dependencies in a processor core;

mapping registers to renamed registers in the schedule; and

stitching register values in and out of another schedule according to the list of register names used but not defined in the schedule, list of registers defined in the schedule, and the rename map of register names.