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Title: US7464246: System and method for dynamic sizing of cache sequential list
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Country: US United States of America

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Inventor: Gill, Binny Sher; San Jose, CA, United States of America
Modha, Dharmendra Shantilal; San Jose, CA, United States of America

Assignee: International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 2008-12-09 / 2004-09-30

Application Number: US2004000954937

IPC Code: Advanced: G06F 12/00;
Core: more...

ECLA Code: G06F12/08B8; G06F12/12B4; S06F12/08B12;

U.S. Class: 711/173; 711/136; 711/170;

Field of Search: 711/173,136,170

Priority Number:
2004-09-30  US2004000954937

Abstract:     A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

Attorney, Agent or Firm: Rogitz, John L. ;

Primary / Asst. Examiners: Shah, Sanjiv; Yu, Jae U

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First Claim:
Show all 4 claims
    1. A method for caching data, comprising:

maintaining a random data list and a sequential data list;

dynamically establishing a desired size for the sequential data list, wherein the establishing act comprises:

empirically determining a marginal utility of adding space to the random data list;

computing a marginal utility of adding space to the sequential data list in terms of a rate of sequential misses; and

based on the computing and determining acts, establishing the desired size of the sequential data list, wherein the empirically determining act comprises determining a rate “s” of sequential misses as the number of sequential misses during a time period defined by two successive cache hits in a bottom portion ΔL of the random data list, wherein the computing act determines the marginal utility to be equal to a number between s/L and 2 s/L, inclusive, wherein s represents a rate of sequential misses for synchronous and asynchronous prefetching and L represents the length of the sequential data list.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (6)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 14pp US5761715  1998-06 Takahashi  Kabushiki Kaisha Toshiba Information processing device and cache memory with adjustable number of ways to reduce power consumption based on cache miss ratio
Buy PDF- 21pp US6141731  2000-10 Beardsley et al.  International Business Machines Corporation Method and system for managing data in cache using multiple data structures
Buy PDF- 23pp US6260115  2001-07 Permut et al.  Storage Technology Corporation Sequential detection and prestaging methods for a disk storage subsystem
Buy PDF- 17pp US6327644  2001-12 Beardsley et al.  International Business Machines Corporation Method and system for managing data in cache
Buy PDF- 14pp US20030105928A1  2003-06 Ash et al.   Method, system, and program for destaging data in cache
Buy PDF- 24pp US20040098541A1  2004-05 Megiddo et al.   System and method for implementing an adaptive replacement cache policy
       
Foreign References: None

Other References:
  • ARC: A Self-Tuning, Low Overhead Replacement Cache by Megiddo & Modha; USENIX File & Storage Tech. Conf.; Mar. 31, 2003, San Francisco, CA.
  • IBM Dossier ARC920020050; Method and System for Adaptive Replacement Cache; Modha and Megiddo, Jan. 29, 2003.


  • Continuity Data:
    Application Number Filed Notes

    US2004000954937 2004-09-30  is a related to the prior publication
         US20060069871A1 issued 2006-03-30  System and method for dynamic sizing of cache sequential list

    US2004000954937 2004-09-30  is a related to the prior publication
         US20080140939A1 issued 2008-06-12  SYSTEM AND METHOD FOR DYNAMIC SIZING OF CACHE SEQUENTIAL LIST

    US2004000954937 2004-09-30  is a related to the prior publication
         US20080140940A1 issued 2008-06-12  SYSTEM AND METHOD FOR DYNAMIC SIZING OF CACHE SEQUENTIAL LIST

    12060431   is a continuation of
    US2008000033105  2008-02-19   (pending) [presumed granted]
         US7533239 issued 2009-05-12   System and method for dynamic sizing of cache sequential list

    12060945   is a continuation of
    US2008000032851  2008-02-18   (pending) [presumed granted]
         US7509470 issued 2009-03-24   System and method for dynamic sizing of cache sequential list

    12033105   is a division of
    >US2004000954937<  2004-09-30   (pending) [presumed granted]
         US7464246 issued 2008-12-09   System and method for dynamic sizing of cache sequential list

    12033105   is a continuation of
    >US2004000954937<  2004-09-30
         US7464246 issued 2008-12-09   System and method for dynamic sizing of cache sequential list

    12032851   is a continuation of
    >US2004000954937<  2004-09-30   (pending) [presumed granted]
         US7464246 issued 2008-12-09   System and method for dynamic sizing of cache sequential list

    12032851   is a continuation of
    >US2004000954937<  2004-09-30
         US7464246 issued 2008-12-09   System and method for dynamic sizing of cache sequential list


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