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Title: |
US7464246:
System and method for dynamic sizing of cache sequential list
[ Derwent Title ]

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Country: |
US United States of America

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Inventor: |
Gill, Binny Sher; San Jose, CA, United States of America
Modha, Dharmendra Shantilal; San Jose, CA, United States of America

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Assignee: |
International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: |
2008-12-09
/ 2004-09-30

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Application Number: |
US2004000954937

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IPC Code: |
Advanced:
G06F 12/00;
Core:
more...

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ECLA Code: |
G06F12/08B8; G06F12/12B4; S06F12/08B12;

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U.S. Class: |
711/173;
711/136;
711/170;

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Field of Search: |
711/173,136,170

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Priority Number: |
| 2004-09-30 |
US2004000954937 |

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Abstract: |
A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

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Attorney, Agent or Firm: |
Rogitz, John L. ;

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Primary / Asst. Examiners: |
Shah, Sanjiv; Yu, Jae U

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INPADOC Legal Status: |
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Family: |
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First Claim:
Show all 4 claims |
1. A method for caching data, comprising: maintaining a random data list and a sequential data list; dynamically establishing a desired size for the sequential data list, wherein the establishing act comprises: empirically determining a marginal utility of adding space to the random data list; computing a marginal utility of adding space to the sequential data list in terms of a rate of sequential misses; and based on the computing and determining acts, establishing the desired size of the sequential data list, wherein the empirically determining act comprises determining a rate “s” of sequential misses as the number of sequential misses during a time period defined by two successive cache hits in a bottom portion ΔL of the random data list, wherein the computing act determines the marginal utility to be equal to a number between s/L and 2 s/L, inclusive, wherein s represents a rate of sequential misses for synchronous and asynchronous prefetching and L represents the length of the sequential data list.

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