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Title: US7473568: Memory-module manufacturing method with memory-chip burn-in and full functional testing delayed until module burn-in
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Country: US United States of America

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16 pages

 
Inventor: Co, Ramon S.; Trabuco Canyon, CA, United States of America
Sun, David; Irvine, CA, United States of America

Assignee: Kingston Technology Corp., Fountain Valley, CA, United States of America
other patents from KINGSTON TECHNOLOGY COMPANY (741845) (approx. 14)
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Published / Filed: 2009-01-06 / 2006-05-17

Application Number: US2006000308869

IPC Code: Advanced: H01L 21/66;
Core: more...

ECLA Code: G01R31/30D; G01R31/3185M5; G11C5/00;

U.S. Class: 438/018; 257/E21.524;

Field of Search: 438/011,18 257/E21.523,E21.524

Priority Number:
2006-05-17  US2006000308869

Abstract:     Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory modules are stressed during burn-in by high temperatures and applied voltages. After burn-in, the memory modules are removed from the memory-module burn-in boards and extensively tested. Functional tests include many test patterns to test all memory locations in the partially-tested memory chips on the memory modules. Tests are performed at corner conditions such as high temperature and voltage. Infant mortality and single-bit faults are detected by the functional tests after module burn-in. The number of insertions into burn-in boards is reduced by the number of memory chips per module minus one, so handling and test costs are reduced.

Attorney, Agent or Firm: Auvinen, Stuart T. ; gPatent LLC ;

Primary / Asst. Examiners: Chaudhari, Chandra;

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First Claim:
Show all 20 claims
    1. A memory-module manufacturing method comprising:

receiving partially-tested memory chips, wherein the partially-tested memory chips are packaged dice that have not been fully tested to detect all defects;

soldering the partially-tested memory chips onto module substrates to create assembled memory modules;

inserting the assembled memory modules into module sockets on memory-module burn-in boards;

placing the memory-module burn-in boards into a burn-in oven;

stressing the assembled memory modules and the partially-tested memory chips soldered to the module substrates of the assembled memory modules by heating the assembled memory modules in the burn-in oven for a burn-in period of time;

removing the memory-module burn-in boards from the burn-in oven after the burn-in period of time and extracting the assembled memory modules from the memory-module burn-in boards as burned-in memory modules; and

fully testing the burned-in memory modules by applying extensive test patterns to the burned-in memory modules;

wherein the extensive test patterns test for possible defects that were not detected in the partially-tested memory chips;

whereby partially-tested memory chips are soldered into assembled memory modules that are burned-in and fully tested.



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Forward References: Show 1 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (1)   |   Backward references (14)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 19pp US5532612  1996-07 Liang   Methods and apparatus for test and burn-in of integrated circuit devices
Buy PDF- 51pp US5539652  1996-07 Tegethoff  Hewlett-Packard Company Method for manufacturing test simulation in electronic circuit design
Buy PDF- 10pp US5764574  1998-06 Nevill et al.   Method and apparatus for back-end repair of multi-chip modules
Buy PDF- 15pp US6008538  1999-12 Akram et al.  Micron Technology, Inc. Method and apparatus providing redundancy for fabricating highly reliable memory modules
Buy PDF- 14pp US6287878  2001-09 Maeng et al.  Samsung Electronics Co., Ltd. Method of fabricating chip scale package
Buy PDF- 9pp US6384613  2002-05 Cheng et al.  AMIC Technology, Inc. Wafer burn-in testing method
Buy PDF- 11pp US6574763  2003-06 Bertin et al.  International Business Machines Corporation Method and apparatus for semiconductor integrated circuit testing and burn-in
Buy PDF- 44pp US20030089978A1  2003-05 Miyamoto et al.   Memory-module and a method of manufacturing the same
Buy PDF- 17pp US20030159278A1  2003-08 Peddle   Methods and apparatus for fabricating Chip-on-Board modules
Buy PDF- 52pp US20030179635A1  2003-09 Terzioglu et al.   Burn in system and method for improved memory reliability
Buy PDF- 17pp US20050125712A1  2005-06 Co et al.   Manifold-Distributed Air Flow Over Removable Test Boards in a Memory-Module Burn-In System With Heat Chamber Isolated by Backplane
Buy PDF- 14pp US20050189267A1  2005-09 Beffa   Method for sorting integrated circuit devices
Buy PDF- 40pp US20060023548A1  2006-02 Hiraki et al.   Semiconductor integrated circuit device, memory module, storage device and the method for repairing semiconductor integrated circuit device
Buy PDF- 9pp US20060049844A1  2006-03 Neyer et al.   Method for testing an electric circuit
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

US2006000308869 2006-05-17  is a related to the prior publication
     US20070269911A1 issued 2007-11-22  Memory-Module Manufacturing Method with Memory-Chip Burn-In and Full Functional Testing Delayed Until Module Burn-In


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