1. A repairing advanced memory buffer comprising: southbound input means for receiving packets over southbound serial lanes from a host processor;
southbound output means for transmitting packets over southbound serial lanes to a downstream memory module;
southbound re-timer means, coupled between the southbound input means and the southbound output means, for re-timing packets received by the southbound input means for transmission over the southbound output means;
northbound input means for receiving packets over northbound serial lanes from the downstream memory module;
northbound output means for transmitting packets over northbound serial lanes toward the host processor;
northbound re-timer means, coupled between the northbound input means and the northbound output means, for re-timing packets received by the northbound input means for transmission over the northbound output means;
memory controller means for generating local control signals to memory chips on a local memory module containing the repairing advanced memory buffer;
packet extract means, coupled between the southbound re-timer means and the memory controller means, for extracting commands, address and data from packets received over the southbound input means from the host processor;
packet generation means, coupled between the northbound re-timer means and the memory controller means, for generating packets for transmission over the northbound output means to the host processor;
wherein the packets generated by the packet generation means contain data read from the memory chips by the memory controller means for address locations within the memory chips that are not defective address locations;
repair address buffer means for storing repair addresses, the repair addresses identifying address locations within the memory chips that are defective address locations; and
repair controller means, coupled to the repair address buffer means and to the memory controller means, for disabling access of the memory chips by the memory controller means for repair addresses,
whereby access of memory chips is disabled for repair addresses.
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