Flash / phase-change memory in multi-ring topology using serial-link packet interface (US7475174)


	Parent Case:			RELATED APPLICATION This application is a continuation-in-part (CIP) of the co-pending application for “PCI Express-Compatible Controller and Interface for Flash Memory”, U.S. Ser. No. 10/803,597, filed Mar. 17, 2004. This application is also related to “Serial Interface to Flash Memory Chip using PCI-Express-Like Packets and Packet Data for Partial-page Writes”, U.S. Pat. No. 7,130,958, filed Feb. 9, 2004.
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	First Claim: Show all 20 claims			1. A multi-ring serial-bus memory system comprising: a multi-ring memory controller for generating request packets that contain flash commands, and for receiving completion packets in response to the flash commands; a first-ring serial link output of the multi-ring memory controller for outputting request packets to a first ring; a first-ring serial link input of the multi-ring memory controller for receiving completion packets from the first ring in response to request packets sent through the first-ring serial link output; a first ring of serial flash-memory chips, each serial flash-memory chip in the first ring having a serial input and a serial output and a flash-memory array, wherein the serial output of a prior serial flash-memory chip in the first ring is connected to the serial output of a following serial flash-memory chip in the first ring, and wherein the serial input of an initial serial flash-memory chip in the first ring is connected to the first-ring serial link output, and wherein the serial output of a last serial flash-memory chip in the first ring is connected to the first-ring serial link input; a second-ring serial link output of the multi-ring memory controller for outputting request packets to a second ring; a second-ring serial link input of the multi-ring memory controller for receiving completion packets from the second ring in response to request packets sent through the second-ring serial link output; a second ring of serial flash-memory chips, each serial flash-memory chip in the second ring having a serial input and a serial output and a flash-memory array, wherein the serial output of a prior serial flash-memory chip in the second ring is connected to the serial output of a following serial flash-memory chip in the second ring, and wherein the serial input of an initial serial flash-memory chip in the second ring is connected to the second-ring serial link output, and wherein the serial output of a last serial flash-memory chip in the second ring is connected to the second-ring serial link input; and a bypassing transceiver in each serial flash-memory chip, the bypassing transceiver comparing a device identifier of a request packet to a current device identifier for the serial flash-memory chip and bypassing and retransmitting the request packet through the serial output when the device identifier mismatches the current device identifier, and decoding the request packet and processing a flash command to generate a completion packet for transmission over the serial output when the device identifier matches the current device identifier, whereby request packets and completion packets are bypassed by serial flash-memory chips in rings connected to the multi-ring memory controller.
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U.S. References:

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