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Title: US7477526: Branching fully-buffered memory-module with two downlink and one uplink ports
[ Derwent Title ]


Country: US United States of America

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15 pages

 
Inventor: Co, Ramon S.; Trabuco Canyon, CA, United States of America 92679

Assignee: None

Published / Filed: 2009-01-13 / 2005-12-29

Application Number: US2005000306481

IPC Code: Advanced: H05K 1/11;
Core: more...

ECLA Code: G11C5/00;

U.S. Class: 361/803; 711/115; 365/200; 365/201; 714/718;

Field of Search: 361/803 711/115 365/200.201,200,201 714/718

Priority Number:
2005-12-29  US2005000306481

Abstract:     A branching fully-buffered memory module has one uplink port and two downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the two downlink ports to two branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory module has re-timing and re-synchronizing buffers that repeat frames to the two downlink ports. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin count. Sync patterns are added to the start of frames to detect any collisions on bidirectional lines. Point-to-point bus segments have only two endpoints despite branching by the branching AMB. Latency from the host processor to the last memory module is reduced by branching compared with a serial daisy-chain of memory modules.

Attorney, Agent or Firm: Auvinen, Stuart T. ; gPatent LLC ;

Primary / Asst. Examiners: Reichard, Dean A.; Chen, Xiaoliang

Family: None

First Claim:
Show all 20 claims
    1. A branching fully-buffered memory module comprising:

a substrate containing wiring traces for conducting signals;

a plurality of contact pads along a first edge of the substrate, the plurality of contact pads for mating with a memory module socket on a motherboard;

a plurality of memory chips mounted on the substrate for storing host data from a host on the motherboard;

a branching Advanced Memory Buffer (AMB) mounted on the substrate for buffering the host data to and from the plurality of memory chips;

uplink contact pads, in the plurality of contact pads, that carry southbound uplink frames of the host data generated by the host for writing to the plurality of memory chips or for writing to downstream memory modules, and that carry northbound uplink frames of host data read from the plurality of memory chips or read from downstream memory modules toward the host;

first downlink contact pads, in the plurality of contact pads, that carry first southbound downlink frames of the host data generated by the host for writing to a first plurality of memory chips in a first downstream memory module in a first branch, and that carry first northbound downlink frames of host data read from the first plurality of memory chips in the first downstream memory module in the first branch;

second downlink contact pads, in the plurality of contact pads, that carry second southbound downlink frames of the host data generated by the host for writing to a second plurality of memory chips in a second downstream memory module in a second branch, and that carry second northbound downlink frames of host data read from the second plurality of memory chips in the second downstream memory module in the second branch;

wherein the branching AMB connects through the wiring traces to the uplink contact pads, to the first downlink contact pads, to the second downlink contact pads, and to the plurality of memory chips;

wherein the plurality of memory chips have data lines that carry the host data and connect to the branching AMB but are isolated from the uplink contact pads, from the first downlink contact pads, and from the second downlink contact pads by the branching AMB;

a replicator, in the branching AMB, for copying the southbound uplink frames received from the uplink contact pads to the first downlink contact pads to generate the first southbound downlink frames, and for copying the southbound uplink frames received from the uplink contact pads to the second downlink contact pads to generate the second southbound downlink frames; and

a stream combiner, in the branching AMB, for transferring the first northbound downlink frames received from the first downlink contact pads to the uplink contact pads to generate the northbound uplink frames, and for transferring the second northbound downlink frames received from the second downlink contact pads to the uplink contact pads to generate the northbound uplink frames,

whereby the branching fully-buffered memory module replicates southbound uplink frames to generate both the first southbound downlink frames to the first branch of the first downstream memory module and the second southbound downlink frames to the second branch of the second downstream memory module.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (10)   |   Citation Link

Buy
PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 18pp US6240101  2001-05 Co et al.  Kingston Technology Co. Bi-directional daisy-chain cascading of network repeaters
Buy PDF- 11pp US6317352  2001-11 Halbert et al.  Intel Corporation Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
Buy PDF- 16pp US6493250  2002-12 Halbert et al.  Intel Corporation Multi-tier point-to-point buffered memory interface
Buy PDF- 10pp US6553450  2003-04 Dodd et al.  Intel Corporation Buffer to multiply memory interface
Buy PDF- 12pp US6625687  2003-09 Halbert et al.  Intel Corporation Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
Buy PDF- 15pp US7197676  2007-03 Co et al.  Kingston Technology Corp. Loop-Back Memory-Module Extender Card for Self-Testing Fully-Buffered Memory Modules
Buy PDF- 17pp US7277337  2007-10 Co et al.  Kingston Technology Corp. Memory module with a defective memory chip having defective blocks disabled by non-multiplexed address lines to the defective chip
Buy PDF- 15pp US7379361  2008-05 Co et al.  Kingston Technology Corp. Fully-buffered memory-module with redundant memory buffer in serializing advanced-memory buffer (AMB) for repairing DRAM
Buy PDF- 20pp US7389381  2008-06 Co   Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules
Buy PDF- 171pp US20050271072A1  2005-12 Anderson et al.   High data rate interface apparatus and method
       
Foreign References: None

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