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Title: US7480303: Pseudo-ethernet switch without ethernet media-access-controllers (MAC's) that copies ethernet context registers between PCI-express ports
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Country: US United States of America

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20 pages

 
Inventor: Ngai, Henry P.; Coto De Caza, CA, United States of America

Assignee: Pericom Semiconductor Corp., San Jose, CA, United States of America
other patents from PERICOM SEMICONDUCTOR CORP. (713978) (approx. 58)
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Published / Filed: 2009-01-20 / 2005-05-16

Application Number: US2005000908515

IPC Code: Advanced: H04L 12/28; H04L 12/56;
Core: more...

ECLA Code: H04L12/56Q1; H04L12/56S8A; H04L29/06K; T04L12/56Q5; T04L12/56S1A; T04L12/56S1C;

U.S. Class: 370/395.5; 370/401;

Field of Search: 370/395.5,401,402,422

Priority Number:
2005-05-16  US2005000908515

Abstract:     A Pseudo-Ethernet switch has a routing table that uses Ethernet media-access controller (MAC) addresses to route Ethernet packets through a switch fabric between an input port and an output port. However, the input port and output port have Peripheral Component Interconnect Express (PCIE) interfaces that read and write PCI-Express packets to and from host-processor memories. When used in a blade system, host processor boards have PCIE physical links that connect to the PCIE ports on the Pseudo-Ethernet switch. The Pseudo-Ethernet switch does not have Ethernet MAC and Ethernet physical layers, saving considerable hardware. The switch fabric can be a cross-bar switch or can be a shared memory that stores Ethernet packet data embedded in the PCIE packets. Write and read pointers for a buffer storing an Ethernet packet in the shared memory can be passed from input to output port to perform packet switching.

Attorney, Agent or Firm: Auvinen, Stuart T. ; gPatent LLC ;

Primary / Asst. Examiners: Shah, Chirag G; Nguyen, Minh-Trang

INPADOC Legal Status: Show legal status actions

Family: None

First Claim:
Show all 11 claims
    1. A dual-protocol switch comprising:

a switch fabric for routing a primary-protocol packet from an input port to a selected output port in response to a primary-protocol destination address of the primary-protocol packet, the primary-protocol destination address determining the selected output port in a plurality of output ports for the primary-protocol packet;

a plurality of external buses for connecting the dual-protocol switch to a plurality of hosts, each external bus in the plurality of external buses for connecting to a host in the plurality of hosts;

wherein the plurality of external buses carry secondary-protocol packets that encapsulate at least portions of primary-protocol packets;

wherein the secondary-protocol packets are formatted for a second protocol while the primary-protocol packets are formatted for a primary protocol, the second protocol and the primary protocol being different network protocols;

a plurality of input ports, each input port for receiving secondary-protocol packets from an external bus in the plurality of external buses, the secondary-protocol packets encapsulating the primary-protocol packets for transport over the external bus;

an input packet memory, for each input port, for storing primary-protocol packets encapsulated in the secondary-protocol packets sent over the external bus;

a secondary-protocol interface for each input port, the secondary-protocol interface transferring the secondary-protocol packets from a memory on the host, over the external bus to the input packet memory for the input port using secondary packets specified by the second protocol; and

a switch controller that receives the primary-protocol destination address extracted by an input port from the primary-protocol packet embedded inside the secondary-protocol packet, the switch controller determining a route through the switch fabric from the input port to the selected output port that is selected by the primary-protocol destination address;

wherein the secondary-protocol packets operate within a single host address space for a single host;

wherein the primary-protocol packets operate within multiple address spaces for a plurality of hosts;

wherein the primary protocol is Ethernet and the second protocol is Peripheral Component Interconnect (PCI), PCI-Express, (PCIE), or an extension of PCI or PCIE, and wherein the primary-protocol destination address is an Ethernet media-access controller (MAC) address,

whereby the second protocol is a single-address-domain protocol while the primary protocol is a multiple-address-domain protocol, and whereby the dual-protocol switch has PCI-Express ports but switches Ethernet packets using Ethernet MAC addresses, and whereby primary-protocol packets are routed through the switch fabric using the primary-protocol destination address, while input and output ports transfer over the plurality of external buses secondary-protocol packets that encapsulate the primary-protocol packets.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (18)   |   Citation Link

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PDF
Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 20pp US5748911  1998-05 Maguire et al.  Compaq Computer Corporation Serial bus system for shadowing registers
Buy PDF- 21pp US6094700  2000-07 Deschepper et al.  Compaq Computer Corporation Serial bus system for sending multiple frames of unique data
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Foreign References: None

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