 |
 |
|
|
|
|
Title: |
US7487320:
Apparatus and system for dynamically allocating main memory among a plurality of applications
[ Derwent Title ]

|
Country: |
US United States of America

|
| |
Inventor: |
Bansal, Sorav; Stanford, CA, United States of America
McKenney, Paul Edward; Beaverton, OR, United States of America
Modha, Dharmendra Shantilal; San Jose, CA, United States of America

|
Assignee: |
International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
News, Profiles, Stocks and More about this company

|
Published / Filed: |
2009-02-03
/ 2004-12-15

|
Application Number: |
US2004000014529

|
IPC Code: |
Advanced:
G06F 12/00;
G06F 13/00;
G06F 13/28;
Core:
G06F 13/20;
more...

|
ECLA Code: |
G06F12/12B; G06F12/12B2; G06F12/12B4B;

|
U.S. Class: |
711/170;
711/133;

|
Field of Search: |
711/170,133,159,154,105,104

|
Priority Number: |
| 2004-12-15 |
US2004000014529 |

|
Abstract: |
An apparatus and system are disclosed for dynamically allocating main memory among applications. The apparatus includes a cache memory module configured to maintain a first list and a second list, each list having a plurality of pages, and a resize module configured to resize the cache by adaptively selecting the first or second list and subtracting pages from or adding pages to the selected list. The system includes the apparatus and a cache replacement module configured to adaptively distribute a workload between the first list and the second list.

|
Attorney, Agent or Firm: |
Kunzler & McKenzie ;

|
Primary / Asst. Examiners: |
Kim, Matt; Birkhimer, Christopher D

|
INPADOC Legal Status: |
None
Family Legal Status Report

|
Family: |
Show 3 known family members

|
First Claim:
Show all 13 claims |
1. An apparatus to dynamically allocate main memory among a plurality of virtual operating systems, the apparatus comprising: a cache memory module comprising an allocation of very large scale integration random access memory circuits for a virtual operating system, the cache memory module maintaining at least a first list and a second list, each list configured to store a plurality of pages, the first list containing pages requested only once since a last removal of a page from the first list and the second list containing pages requested at least twice since a last removal of pages from the second list, each list having a T portion and a B portion, the cache memory module having an allocation of pages; and a resize module comprising computer instructions stored in a memory device, executing on a processor, that shrinks the allocation of the cache memory module by setting a size of the T portion of the first list to a new allocation, discarding pages from the T portions of the first and second lists until a sum of sizes of the T portions of the first and second lists is less than the new allocation, and if a sum of sizes of the T and B portions of the first list is greater than the new allocation, removing pages from the B portion of the first list until a sum of sizes of the B portions of the first and second lists is less than the new allocation else removing pages from the B portion of the second list until the sum of the sizes of the B portions of the first and second lists is less than the new allocation.

|
Background / Summary: |
Show background / summary

|
Drawing Descriptions: |
Show drawing descriptions

|
Description: |
Show description

|
 |
 |
|
|
|
|
Foreign References: |
None

|
Other References: |
Nimrod Megiddo and Dharmendra S. Modha, ARC: A Self-Tuning, Low Overhead Replacement Cache, 2003, USENIX Association, FAST '03: 2nd USENIX Conference on File and Storage Technologies, pp. 115-130.
Paul Horan, Page Size VS Cache Size, Feb. 13, 2001, Google Groups, http://groups.google.com/?hl=en, search string (cache+“empty pages”).
Wepopedia, “Cache”, Sep. 16, 2004, p. 1-5 http://www.webopedia.com/TERM/c/cache.html.
Wepopedia, “Operating System”, Jan. 4, 2002, p. 1-5 http://www.webopedia.com/TERM/o/operating—system.html.
Sorav Bansal and Dharmendra S. Modha, “ARC Refinements”, pp. 1-3. Jul. 16, 2003.
Nimrod Megiddo, et al., “ARC: A Self-Tuning, Low Overhead Replacement Cache” USENIX File & Storage Technologies Conference (FAST), pp. 1-16, Mar. 31, 2003.
Sorav Bansal, et al., “CAR: Clock with Adaptive Replacement”, Stanford University, IBM Almaden Research Center, pp. 1-14.

|
Continuity Data: |
| Application Number | Filed | Notes |
|
|
US2004000014529 | 2004-12-15 | is a
related to the prior publication |
| |
US20060129782A1 issued 2006-06-15 Apparatus, system, and method for dynamically allocating main memory among a plurality of applications
|
|
|
|
12265522 | | is a
continuation of |
|
>US2004000014529<
| 2004-12-15 |
(pending)
[presumed granted]
|
| |
US7487320 issued 2009-02-03 Apparatus and system for dynamically allocating main memory among a plurality of applications
|
|

|


|
Nominate this for the Gallery...

|
|