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Title: US7487428: Fully-buffered memory-module with error-correction code (ECC) controller in serializing advanced-memory buffer (AMB) that is transparent to motherboard memory controller
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Country: US United States of America

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16 pages

 
Inventor: Co, Ramon S.; Trabuco Canyon, CA, United States of America
Sun, David; Irvine, CA, United States of America

Assignee: Kingston Technology Corp., Fountain Valley, CA, United States of America
other patents from KINGSTON TECHNOLOGY COMPANY (741845) (approx. 14)
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Published / Filed: 2009-02-03 / 2006-07-24

Application Number: US2006000309298

IPC Code: Advanced: G11C 29/00;
Core: more...

ECLA Code: G06F11/10M2D;

U.S. Class: 714/763;

Field of Search: 714/763

Priority Number:
2006-07-24  US2006000309298

Abstract:     An error-correcting fully-buffered memory module can detect and correct some errors in data read from memory chips. An error correction code ECC controller is added to the Advanced Memory Buffer (AMB) on the memory module that fully buffers memory requests sent as serial packets. The error correction controller generates ECC bits for write data, and both the ECC bits and the write data are written to the memory chips by a DRAM controller in the AMB. During reads, an ECC checker generates a syndrome and can activate an error corrector to correct data or signal a non-correctable error. The corrected data is formed into serial packets sent back to the motherboard by the AMB. Configuration data for the ECC controller could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to error-correction configuration registers on the AMB during power-up.

Attorney, Agent or Firm: Auvinen, Stuart T. ; g Patent LLC ;

Primary / Asst. Examiners: Lamarre, Guy J;

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First Claim:
Show all 22 claims
    1. An error-correcting fully-buffered memory module comprising:

a substrate having wiring traces formed thereon for conducting signals;

contact pads along a lower edge of the substrate, the contact pads for mating with a memory module socket on a motherboard;

a buffer chip mounted to the substrate;

a packet interface, in the buffer chip, for receiving incoming serial packets from the motherboard through the contact pads, and for generating outgoing serial packets for transmission through the contact pads to the motherboard;

memory chips mounted to the substrate, the memory chips having address, data, and control inputs that are isolated from the contact pads by the buffer chip;

a memory controller, in the buffer chip, for generating address, data, and control signals to the memory chips in response to the incoming serial packets received from the motherboard, and for reading read-data and error-correction code (ECC) bits from the memory chips in response to a read command extracted from the incoming serial packets; and

an error-correction controller, coupled to the memory controller, for generating the ECC bits from write-data extracted from incoming serial packets by the packet interface, and for checking the ECC bits read from the memory chips by the memory controller;

wherein the memory chips store the ECC bits generated by the error-correction controller and the write-data extracted by the packet interface,

whereby the ECC bits are locally generated by the error-correction controller and locally checked on the error-correcting fully-buffered memory module.



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Forward References: Show 1 U.S. patent(s) that reference this one

       
U.S. References: Go to Result Set: All U.S. references   |  Forward references (1)   |   Backward references (12)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 11pp US5612964  1997-03 Haraszti   High performance, fault tolerant orthogonal shuffle memory and method
Buy PDF- 11pp US6345374  2002-02 Tsuda  Sanyo Electric Co., Ltd. Code error correcting apparatus
Buy PDF- 30pp US7007130  2006-02 Holman  Intel Corporation Memory system including a memory module having a memory module controller interfacing between a system memory controller and memory devices of the memory module
Buy PDF- 24pp US7010642  2006-03 Perego et al.  Rambus Inc. System featuring a controller device and a memory module that includes an integrated circuit buffer device and a plurality of integrated circuit memory devices
Buy PDF- 12pp US7020825  2006-03 Watanabe et al.  Sanyo Electric Co., Ltd. Data processor with serial transfer of control program
Buy PDF- 37pp US7032158  2006-04 Alvarez, II et al.  Quickshift, Inc. System and method for recognizing and configuring devices embedded on memory modules
Buy PDF- 14pp US20050246594A1  2005-11 Co et al.   Extender Card for Testing Error-Correction-Code (ECC) Storage Area on Memory Modules
Buy PDF- 14pp US20060020740A1  2006-01 Bartley et al.   Multi-node architecture with daisy chain communication link configurable to operate in unidirectional and bidirectional modes
Buy PDF- 45pp US20060047899A1  2006-03 Ilda et al.   Storage device control apparatus
Buy PDF- 13pp US20060075282A1  2006-04 Borkenhagen et al.   Diagnostic interface architecture for memory device
Buy PDF- 14pp US20060090112A1  2006-04 Cochran et al.   Memory device verification of multiple write operations
Buy PDF- 15pp US20060095592A1  2006-05 Borkenhagen   Multi-channel memory architecture for daisy chained arrangements of nodes with bridging between memory channels
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

US2006000309298 2006-07-24  is a related to the prior publication
     US20080022186A1 issued 2008-01-24  Fully-Buffered Memory-Module with Error-Correction Code (ECC) Controller in Serializing Advanced-Memory Buffer (AMB) that is transparent to Motherboard Memory Controller


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