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Title: |
US7500050:
Wise ordering for writes—combining spatial and temporal locality in write caches for multi-rank storage
[ Derwent Title ]

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Country: |
US United States of America

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Inventor: |
Gill, Binny Sher; Auburn, MA, United States of America
Modha, Dharmendra Shantilal; San Jose, CA, United States of America

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Assignee: |
International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: |
2009-03-03
/ 2006-03-20

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Application Number: |
US2006000384890

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IPC Code: |
Advanced:
G06F 12/00;
Core:
more...

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ECLA Code: |
G06F12/12B4;

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U.S. Class: |
711/113;
711/130;

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Field of Search: |
711/113

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Priority Number: |
| 2006-03-20 |
US2006000384890 |

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Abstract: |
A storage system has a storage controller for an array of storage disks, the array being ordered in an sequence of write groups. A write cache is shared by the disks. The storage controller temporarily stores write groups in the write cache responsive to write groups being written to their respective arrays. The write groups are assigned to a global queue ordered by ages. The controller selects a quantity of write groups for attempted destaging to the arrays responsive to a predetermined high threshold for the global queue and to sizes and the ages of the write groups in the global queue, and allocates the selected quantity among the arrays responsive to quantities of certain ones of the write groups in the global queue. Write groups are destaged to respective arrays responsive to the selected allocation quantity for the array and the sequences of the write groups in the arrays.

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Attorney, Agent or Firm: |
England, Anthony V. S. ;
Apello, Jeffrey P. ;

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Primary / Asst. Examiners: |
Bragdon, Reginald G; Ruiz, Aracelis

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INPADOC Legal Status: |
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Parent Case: |
CROSS-REFERENCE
This application is related to U.S. patent application Ser. No. 11/384,939, filed Mar. 20, 2006, titled Wise Ordering For Writes—Combining Spatial and Temporal Locality in Write caches, and the related application is hereby incorporated herein by reference.

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Family: |
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First Claim:
Show all 7 claims |
1. A method of destaging a computer readable write cache in a storage system having an number of arrays of storage disks, such an array having a rank of data ordered in a sequence of write groups, wherein the write cache is shared by the disk arrays, the method comprising the steps of: a) storing ones of the write groups in the write cache temporarily responsive to the ones of the write groups being written to their respective arrays; b) assigning the write groups stored in the write cache to a global queue, wherein the write groups in the global queue are ordered by ages of the write groups; c) selecting a quantity of write groups for attempted destaging to the arrays responsive to a predetermined high threshold for the global queue and to sizes and the ages of the write groups in the global queue; d) allocating the selected quantity among the arrays responsive to quantities of certain ones of the write groups in the global queue, so that the arrays have respective allocation quantities of write groups for destaging; and e) destaging ones of the write groups in the write cache to the arrays, wherein write groups are destaged to such an array responsive to i) the selected allocation quantity for the array and ii) the sequences of the write groups in the array.

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Background / Summary: |
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Drawing Descriptions: |
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Description: |
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Foreign References: |
Buy PDF |
Publication |
Date |
IPC Code |
Assignee |
Title |
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JP2001249835A
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2002-09 |
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Other References: |
Lee, Jung-Hoon et al., Application-adaptive intelligent cache memory system, ACM Transactions on Embedded Computing Systems (TECS), ACM Transactions on Embedded Computing Systems (TECS), vol. 1, Issue 1 (Nov. 2002), pp. 56-78.
Panda, P.R. et al., Data and memory optimization techniques for embedded systems, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 6, Issue 2 (Apr. 2001), pp. 149-206.
Song, Yonghong et al., “Data Locality Enhancement by Memory Reduction,” Proceedings of the 15th international conference on Supercomputing, Jun. 16-21, 2001, Sorrento, Italy, pp. 50-64, https://www.cs.purdue.edu/homes/li/draft/ics01.pdf.
Lee, Jung-Hoon et al., “Application-adaptive intelligent cache memory system,” ACM Transactions on Embedded Computing Systems (TECS), ACM Transactions on Embedded Computing Systems (TECS), vol. 1, Issue 1 (Nov. 2002), pp. 56-78, http://wotan.liu.edu/docis/lib/sisl/rclis/dbl/atemcs/(2002)1%253A1%253C56%253AAICMS%253E/supercom.yonsei.ac.kr%252Fpaper%252FACM-format-final.pdf.
Sermulins, Janis et al., “Cache Aware Optimization of Stream Programs, ” Proceedings of the 2005 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, Jun. 15-27, 2005, Chicago, vol 40 Issue 7, pp. 115-126, http://web.mit.edu/rabbah/www/docs/sermulins-lctes-2005.pdf.
Panda, P.R.et al., “Data and memory optimization techniques for embedded systems,” ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 6, Issue 2 (Apr. 2001), pp. 149-206, http://www.ee.ucla.edu/˜ingrid/Courses/Reading/p149-pandaACM2001.pdf.
Marathe, Jaydeep et al., “Metric: Tracking down inefficiencies in the memory hierarchy via binary rewriting,” Performance monitoring session, ACM International Conference Proceeding Series, vol. 37, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, Mar. 23-26, 2003, pp. 289-300, http://www.csl.cornell.edu/˜sam/papers/cgo03.pdf.

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Continuity Data: |
| Application Number | Filed | Notes |
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US2006000384890 | 2006-03-20 | is a
related to the prior publication |
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US20070220200A1 issued 2007-09-20 Wise ordering for writes - combining spatial and temporal locality in write caches for multi-rank storage
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