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Title: US7502890: Method and apparatus for dynamic priority-based cache replacement
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Country: US United States of America

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Inventor: Kailas, Krishnan Kunjunny; Tarrytown, NY, United States of America
Ravindran, Rajiv Alazhath; Ann Arbor, MI, United States of America
Sura, Zehra; Yorktown Heights, NY, United States of America

Assignee: International Business Machines Corporation, Armonk, NY, United States of America
other patents from INTERNATIONAL BUSINESS MACHINES CORPORATION (280070) (approx. 44,393)
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Published / Filed: 2009-03-10 / 2006-07-07

Application Number: US2006000482924

IPC Code: Advanced: G06F 12/12;
Core: more...

ECLA Code: G06F12/12B6;

U.S. Class: 711/133;

Field of Search: Non/00e

Priority Number:
2006-07-07  US2006000482924

Abstract:     One embodiment of the present method and apparatus for dynamic priority-based cache replacement includes selectively assigning relative priority values to at least a subset of data items in the cache memory system, fetching a new data item to load into the cache memory system, the data item being associated with a priority value, and selecting an existing data item from the cache memory system to replace with the new data item, in accordance with the relative priority values and the priority value of the new data item.

Primary / Asst. Examiners: Bragdon, Reginald G; Vo, Thanh D

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First Claim:
Show all 20 claims
    1. A method for managing data in a cache memory system, the method comprising:

assigning relative priority values to at least a subset of data items in the cache memory system, wherein the assigning comprises:

identifying one or more regions of code that require prioritized data items;

identifying one or more load/store instructions associated with the one or more regions of code;

identifying one or more data items accessed by the one or more load/store instructions; and

tagging the one or more data items to reflect relative priorities of the one or more data items by executing an address capture load/store instruction that updates priority tag fields of entries in a tag directory that correspond to the one or more data items, wherein the address capture load/store instruction comprises:

a priority tag loaded to a priority tag register at a beginning of a given one of the one or more regions of code; and

an update priority range instruction inserted at an end of the given one of the one or more regions of code;

fetching a new data item to load into the cache memory system, the new data item being associated with a priority value; and

selecting an existing data item from the cache memory system to replace with the new data item, in accordance with the relative priority values and the priority value associated with the new data item.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (9)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 21pp US5924116  1999-07 Aggarwal et al.  International Business Machines Corporation Collaborative caching of a requested object by a lower level node as a function of the caching status of the object at a higher level node
Buy PDF- 30pp US5956744  1999-09 Robertson et al.  Texas Instruments Incorporated Memory configuration cache with multilevel hierarchy least recently used cache entry replacement
Buy PDF- 14pp US6012126  2000-01 Aggarwal et al.  International Business Machines Corporation System and method for caching objects of non-uniform size using multiple LRU stacks partitions into a range of sizes
Buy PDF- 9pp US6292871  2001-09 Fuente  International Business Machines Corporation Loading accessed data from a prefetch buffer to a least recently used position in a cache
Buy PDF- 23pp US6378042  2002-04 Henderson et al.  Fast-Chip, Inc. Caching associative memory
Buy PDF- 13pp US6532520  2003-03 Dean et al.  International Business Machines Corporation Method and apparatus for allocating data and instructions within a shared cache
Buy PDF- 7pp US6785770  2004-08 Hoogerbrugge et al.  Koninklijke Philips Electronics N.V. Data processing apparatus with a cache memory and method of using such an apparatus
Buy PDF- 20pp US20040078516A1  2004-04 Henderson et al.   Caching associative memory using non-overlapping data
Buy PDF- 10pp US20050114605A1  2005-05 Iyer et al.   Methods and apparatus to process cache allocation requests based on priority
       
Foreign References: None

Other References:
  • Prabhat Jain, Srinivas Devadas, Larry Rudolph, “Controlling Cache Pollution in Prefetching With Software-assisted Cache Replacement”, CSG Memo 462, MIT, Jul. 2001.
  • Zhenlin Wang, Kathryn McKinley, Arnold Rosenberg, Charles Weems, “Using the Compiler to Improve Cache Replacement Decisions”, PACT 2002.
  • Prabhat Jain, Srinivas Devdas, “Software-assisted Cache Replacement Mechanisms for Embedded Systems”, Proceedings of the Int'l Conference on Computer-Aided Design, Nov. 2001.
  • Jennifer Sartor, Subramanian Venkiteswaran, Kathryn McKinley, Zhenlin Wang, “Cooperative Caching with Keep-Me and Evict-Me”, 9th Annual Workshop on Interaction between Compilers and Computer Architectures {Interact -9}, Feb. 2005.
  • D.B. Kirk “SMART {Strategic Memory Allocation for Real-Time} Cache Design,” Proc. 10th Real-Time Systems Symp., pp. 229-237, Dec. 1989.


  • Continuity Data:
    Application Number Filed Notes

    US2006000482924 2006-07-07  is a related to the prior publication
         US20080010414A1 issued 2008-01-10  Method and apparatus for dynamic priority-based cache replacement


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