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Title: US7533239: System and method for dynamic sizing of cache sequential list
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Country: US United States of America

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Inventor: Gill, Binny Sher; San Jose, CA, United States of America
Modha, Dharmendra Shantilal; San Jose, CA, United States of America

Assignee: International Business Machines Corporation, Armonk, NY, United States of America
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Published / Filed: 2009-05-12 / 2008-02-19

Application Number: US2008000033105

IPC Code: Advanced: G06F 12/00;
Core: more...

ECLA Code: G06F12/08B8; G06F12/12B4; S06F12/08B12;

U.S. Class: 711/173; 711/136; 711/170;

Field of Search: 711/136,170,173

Priority Number:
2008-02-19  US2008000033105
2004-09-30  US2004000954937

Abstract:     A self-tuning, low overhead, simple to implement, locally adaptive, novel cache management policy that dynamically and adaptively partitions the cache space amongst sequential and random streams so as to reduce read misses.

Attorney, Agent or Firm: Rogitz, John L. ;

Primary / Asst. Examiners: Elmore, Stephen C; Yu, Jae U

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Related Applications:
Application Number Filed Patent Pub. Date  Title
US2004000954937 2004-09-30    2008-12-09  System and method for dynamic sizing of cache sequential list


       
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Claim     1. A data system using a least recently used (LRU) caching scheme using synchronous and asynchronous prefetch of data from a data storage device, the system avoiding violation of stack property substantially without incurring additional sequential misses from cache at least in part by determining a marginal utility of adding space to a sequential list to be equal to a number between s/L and 2s/L, inclusive, wherein L represents the length of the sequential list and “s” is a rate of sequential misses, wherein the system executes logic including:

empirically determining a marginal utility of adding space to a random list; and

based on the determining and Empirically determining acts, dynamically establishing a desired size of the sequential list, wherein the logic executes the empirically determining act by determining the rate “s” of sequential misses as the number of se sequential misses during a time period defined by two successive cache hits in a bottom portion ΔL of the random list, and further wherein the system executes logic comprising:

moving at least one newly prefetched group of units of data along with an asynchronous trigger unit of data in the group of units of data to a most recently used (MRU) portion of a sequential data list; and

moving at least some unaccessed units of data in the group of units of data to the MRU portion of the sequential data list.



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U.S. References: Go to Result Set: All U.S. references   |  No patents reference this one   |   Backward references (1)   |   Citation Link

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Patent  Pub.Date  Inventor Assignee   Title
Buy PDF- 20pp US20020010838A1  2002-01 Mowry   PREFETCHING HINTS
       
Foreign References: None

Continuity Data:
Application Number Filed Notes

US2008000033105 2008-02-19  is a related to the prior publication
     US20080140940A1 issued 2008-06-12  SYSTEM AND METHOD FOR DYNAMIC SIZING OF CACHE SEQUENTIAL LIST

12060431   is a continuation of
>US2008000033105<  2008-02-19   (pending) [presumed granted]
     US7533239 issued 2009-05-12   System and method for dynamic sizing of cache sequential list

12033105   is a division of
US2004000954937  2004-09-30   (pending) [presumed granted]
     US7464246 issued 2008-12-09   System and method for dynamic sizing of cache sequential list

12033105   is a continuation of
US2004000954937  2004-09-30
     US7464246 issued 2008-12-09   System and method for dynamic sizing of cache sequential list


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