a reference clock input for receiving a reference clock, wherein the reference clock is a differential clock represented by a difference of signals carried by a true signal line and by a complement signal line;

a first differential clock buffer, receiving the reference clock on a true input and on a complement input, the first differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered reference clock;

a first differential-to-single-ended (DTS) converter, receiving the buffered reference clock on a true input and on a complement input, the first DTS converter generating a combined reference clock signal as a difference of the true input and the complement input;

a second differential clock buffer, receiving a feedback clock on a true input and on a complement input, the second differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered feedback clock;

a second DTS converter, receiving the buffered feedback clock on a true input and on a complement input, the second DTS converter generating a combined feedback clock signal as a difference of the true input and the complement input;

a phase detector having a first input that receives the combined reference clock signal from the first DTS converter and having a second input that receives the combined feedback clock signal from the second DTS converter, the phase detector detecting a phase difference between the combined reference clock signal and the combined feedback clock signal and generating an up signal and a down signal in response to the phase difference detected;

a sensing capacitor for storing charge to generate a sensing voltage;

a first charge pump, activated by the up signal from the phase detector, for charging the sensing capacitor;

a second charge pump, activated by the down signal from the phase detector, for discharging the sensing capacitor;

a voltage-controlled oscillator (VCO) that receives the sensing voltage from the sensing capacitor, the VCO generating the feedback clock with a frequency that is dependent on the sensing voltage, wherein the VCO outputs a true signal and a complement signal for the feedback clock;

an output differential clock buffer, receiving the feedback clock on a true input and on a complement input, the output differential clock buffer sensing a voltage difference between the true input and the complement input and driving a true output and a complement output with a buffered output clock;

a first common-mode sensor, coupled to the first differential clock buffer to sense a first common-mode voltage of the true output and the complement output from the first differential clock buffer;

a second common-mode sensor, coupled to the second differential clock buffer to sense a second common-mode voltage of the true output and the complement output from the second differential clock buffer; and

a first equalizer, receiving the first common-mode voltage from the first common-mode sensor, and receiving the second common-mode voltage from the second common-mode sensor, for generating a second control voltage;

wherein the second control voltage is applied to the second differential clock buffer, the second control voltage adjusting the second common-mode voltage of the true output and the complement output from the second differential clock buffer,