a first demultiplexer receiving a first differential input on a first pair of input lines and generating a first intermediate differential signal on a first intermediate pair of lines and generating a second intermediate differential signal on a second intermediate pair of lines;

a second demultiplexer receiving a second differential input on a second pair of input lines and generating a third intermediate differential signal on a third intermediate pair of lines and generating a fourth intermediate differential signal on a fourth intermediate pair of lines;

a first load-canceling circuit, connected to the first intermediate pair of lines, for compensating for loading on the first intermediate pair of lines;

a first select circuit, responsive to a first select signal in a first state, for enabling the first load-canceling circuit;

a second load-canceling circuit, connected to the second intermediate pair of lines, for compensating for loading on the second intermediate pair of lines;

a second select circuit, responsive to a second select signal in a second state, for enabling the second load-canceling circuit;

a third load-canceling circuit, connected to the third intermediate pair of lines, for compensating for loading on the third intermediate pair of lines;

a third select circuit, responsive to the first select signal not in the first state, for enabling the third load-canceling circuit;

a fourth load-canceling circuit, connected to the fourth intermediate pair of lines, for compensating for loading on the fourth intermediate pair of lines;

a fourth select circuit, responsive to the second select signal not in the second state, for enabling the fourth load-canceling circuit;

a first active mux amplifier, coupled to outputs of the first load-canceling circuit and the third load-canceling circuit, for generating a first switch differential output on a first output pair of lines from the first differential input when the first select signal is in the first state, and for generating the first switch differential output from the second differential input when the first select signal is not in the first state; and

a second active mux amplifier, coupled to outputs of the second load-canceling circuit and the fourth load-canceling circuit, for generating a second switch differential output on a second output pair of lines from the first differential input when the second select signal is in the second state, and for generating the second switch differential output from the second differential input when the second select signal is not in the second state,

whereby differential signals are equalized and multiplexed.