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 Title: |
WO8802148A1:
A TRANSPARENT TRANSLATION METHOD AND APPARATUS FOR USE IN A MEMORY MANAGEMENT UNIT
[ Derwent Title ]
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Country:
Kind: |
WO World Intellectual Property Organization (WIPO)
A1 INTERNATIONAL APPLICATION PUBLISHED WITH INTERNATIONAL SEARCH REPORT i
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| Inventor: |
MOYER, William, C.;
RUPP, Edward, J., II.;
TRISSEL, David, W.;
VEGESNA, Anantakotiraju;
STANPHILL, Russell, C.;
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| Assignee: |
MOTOROLA, INC.
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| Published / Filed: |
1988-03-24
/ 1987-06-08
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| Application Number: |
WO1987US0001341
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| IPC Code: |
Advanced:
G06F 12/10;
Core:
more...
IPC-7:
G06F 12/10;
G06F 12/12;
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| Priority Number: |
| 1986-09-15 |
US1986000908078 |
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| Abstract: |
In a data processing system (10) comprising a central processing unit (CPU) (12), a memory management unit (MMU) (16) and a storage system (14), the MMU (16) translates each of the logical addresses output by CPU (12) to a corresponding physical address in the storage system (14). In the MMU (16), a comparator (32) determines if each logical address is within an address range defined by an address range descriptor stored in a transparent translation register (TTR) (30). If a logical address is found to be within that address range, the MMU (16) is forced to provide that logical address as the corresponding physical address without translation. Selected control signals may be conditionally provided in the event of such a ''transparent'' translation.
[French]
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| INPADOC Legal Status: |
Show legal status actions
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| Designated Country: |
DE FR GB JP KR
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| Family: |
None
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First Claim:
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CLAIMS
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Description
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+ A TRANSPARENT TRANSLATION METHOD AND APPARATUS
FOR USE IN A MEMORY MANAGEMENT UNIT
+ Field of the Invention The subject invention relates generally to memory management units and, more particularly, to a method and apparatus to force a memory management unit to provide each of a plurality of logical addresses within a selected range of logical addresses as a respective physical address without translation.
+ Background Art In data processing systems having virtual memory capabilities, a memory management unit (MMU) is provided to translate each "logical" address in virtual memory as it is output by the data processor to a respective "physical" address in real memory. In general, upon initiation of system operation, the MMU is in a non-translation mode so that each logical address is provided as the respective physical address without translation. After the operating system has initialized all appropriate logical-to-physical address translation information in the MMU or in memory, as the case may be, the MMU can be put into the normal translation mode. Thereafter, the MMU will translate all logical addresses output by the processor to the respective physical addresses according to the translation information established by the operating system.
In some systems, certain portions of the available physical address space are reserved for special functions, such as memory-mapped 1/0, system tables, shared code and the like. To minimize the time necessary to access these reserved portions of physical memory, steps can be taken to "bypass" the MMU. For example, in at least one prior art system, commercially available from Sun Microsystems, Inc., of Mountain View, CA, the MMU includes special address detection hardware which, upon detecting logical addresses within a fixed address range, immediately forces the MMU to gate such logical addresses directly from the logical address bus to the physical address bus without translation or any associated table- walking. Although this technique greatly speeds up the operation of the processor to locations within this fixed Portion of memory, there is no provision for direct access to other portions of the physical memory. Neither is there any mechanism for modifying the physical address of this dedicated portion of memory if such becomes necessary or desirable. Further, this scheme restricts the range of dedicated physical addresses to physically contiguous memory locations.
+ Summary of the Invention Accordingly, it is an object of the present invention to provide a transparent translation mechanism which allows the range of non-translated addresses to be-dynamically changed. Another object of the present invention is to provide a technique whereby the range of non-translated addresses is not restricted to-a set of physically contiguous addresses.
One other object-of the present -invention is to provide a transparent translation mechanism which can be selectively restricted to certain types of access, i.e. reads only, writes only, or both reads and writes.
+ Brief Description of the Drawing Figure 1 illustrates in block diagram form, a data processing system constructed in accordance with the present invention. Figure 2 illustrates in schematic form, the preferred form of the transparent translation register and the comparator shown in Figure 1. ###
Description of the Invention Shown in Figure 1 is a virtual memory type of data processing system 10 comprising a central processing unit (CPU) 12, a storage system 14 and a memory management unit (MMU) 16. In general, supervisor and user programs are stored in the storage system 14, which typically comprises high speed memory and slower speed peripherals such as disks, at respective physical addresses. During operation, the CPU 12 references the instructions and data operands comprising these programs using respective logical addresses. The MMU 16 receives the logical addresses output by the CPU 12 via a logical address bus 18, translates these logical addresses to the corresponding physical-addresses using logical-t6-physical-address translation descriptors stored either within the MMU 16 or within the storage system 14, and forwards the resultant physical addresses to the storage system 14 via a physical address bus 20. In response to receiving each physical address, the storage system 14 allows the CPU 12 to access a respective storage location within the storage system 14 via a data bus 22.
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