 |
|
|
|
|
|
 Title: |
WO9005331A1:
REMOTE LINKABLE COMPUTER BUS
[ Derwent Title ]
|
Country:
Kind: |
WO World Intellectual Property Organization (WIPO)
A1 INTERNATIONAL APPLICATION PUBLISHED WITH INTERNATIONAL SEARCH REPORT i
|
| |
| Inventor: |
SELBY, Howard, W., III;
|
| Assignee: |
SELBY, Howard, W., III
News, Profiles, Stocks and More about this company
|
| Published / Filed: |
1990-05-17
/ 1989-10-23
|
| Application Number: |
WO1989US0004718
|
| IPC Code: |
Advanced:
G06F 13/40;
Core:
more...
IPC-7:
G06F 3/00;
G06F 13/00;
|
| Priority Number: |
| 1988-11-02 |
US1988000266083 |
|
| Abstract: |
A computer bus structure that can be segmented, thereby allowing operation of the computer in multiple locations. Devices, components, and peripherals can be connected to any segment of the bus and function with other devices, components, and peripherals on other segments of the bus.
[French]
|
| INPADOC Legal Status: |
Show legal status actions
Family Legal Status Report
|
| Designated Country: |
AT AU BE BR CH DE FR GB IT JP KR LU NL SE
|
| Family: |
Show 3 known family members
|
First Claim:
Show all claims |
claims 1. A bus structure for transmitting data signals between a plurality of components in a computer system, at least one of said components being disposed at a first location and at least one other of said components being disposed at a second location, said first and second locations being physically remote from one another, said bus structure comprising: a first bus segment disposed at said first location and which can be operatively connected to the components disposed at said first location for transmitting data signals to and from said components disposed at said first location; a second bus segment disposed at said second location and which can be operatively connected to the components disposed at said second location for transmitting data to and from said components disposed at said second location; and first and second bus logic means disposed at said first and second locations, respectively, and operatively connected to said first and second bus segments, respectively, for, in the case of said first bus logic means, establishing a connection between said first and second bus segments and transmitting said data signals via said connection to said second bus segment, and, in the case of said second bus segment logic means, causing said second bus segment to respond to establishment of said connection and transmission of said data signals via said connection by receiving said data signals and transmitting them to any component operatively connected to said second bus segment.
|
Description
Expand description |
+ REMOTE LINKABLE COMPUTER BUS
Backcrround of the Invention
+ Field of the Invention
This invention relates generally to computer buses, and more particularly to a computer bus that a user can readily operate in multiple locations. ###
+ Summary of the Invention These and other objects of the invention are accomplished in accordance with the principles of the invention by use of a computer bus that can be located in more than one location and which can be remotely linked together so that the bus operates as a single unified bus. Any components or peripherals that are connected to the bus can be connected to any segment of the bus. To the user, the bus operates as one unified bus, even though the bus is physically present in several locations.
An instruction from the central processing unit (CPU) of the computer will automatically be sent to a remote bus segment of the computer if the target device for the instruction is connected to the remote segment of the bus. Alternatively, instructions or data emanating from the device connected to the remote segment of the bus will be sent back to the CPU for processing. Electronic signals being transmitted via the bus transit the remote linkable computer bus by way of bus bridges. The bus bridge forms the communication link between bus segments in different locations. A variety of means can be used to form the bus bridge including connectors, cables, modems and telephone lines, electromagnetic transmissions, etc. There may be several bus bridges available at the same time. The computer selects the most reliable bridge for the bus based on the bus bridges available to the computer and a user-determined hierarchy of bus bridges (e.g., traditional telephone line selected in preference to a cellular telephone connection). The remote linkable computer bus employs a bus manager program (i.e., a program residing in the computer's main memory) to control operation of the bus. The bus manager program maintains an inventory of bus segments and of items connected to the various segments of the remote linkable bus. In addition, the bus manager program configures the communication links between bus segments. Finally, the-bus manager program provides for signal interaction between bus segments. The remote linkable bus operates in such a way that the user does not have to change how he or she uses the computer in order to access the entire bus; whether in the office or on the road, the full functionality of the bus is available to the user.
+ Brief Description of the Drawings FIG. 1 is a block diagram of the remote linkable computer bus of this invention.
FIGS. 2A and 2B (sometimes collectively referred to as FIG. 2) are block diagrams showing several illustrative configurations of device, component, and peripheral connection to the remote linkable computer bus of this invention.
+ Detailed Description of the Preferred-Embodiments Referring now to the drawings, wherein like numerals represent like or corresponding elements throughout-the several views, there is shown in FIG. 1 a block diagram of the remote linkable computer bus.
Because the remote linkable computer bus 10 can reside in several locations, it is tied together through remote link 12 to form a unified bus. one segment of the bus that resides with the computer's central processing unit (CPU) 14 is referred to as the local bus segment loa of the remote linkable bus. CPU 14 is typically any suitable microprocessor such as a conventional Intel 80286 or Intel 80386 microprocessor.
|
|
